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Commit f1017969 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
Browse files

clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6 



The pll6 has a /4 output that is used as an input to the ahb mux clock.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 934fe5f4

drivers/clk/sunxi/clk-sunxi.c

+2 −1
Original line number Diff line number Diff line
@@ -1088,11 +1088,12 @@ static const struct divs_data pll5_divs_data __initconst = { 


static const struct divs_data pll6_divs_data __initconst = {

	.factors = &sun4i_pll6_data,

	.ndivs = 3,

	.ndivs = 4,

	.div = {

		{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */

		{ .fixed = 2 }, /* P, other */

		{ .self = 1 }, /* base factor clock, 2x */

		{ .fixed = 4 }, /* pll6 / 4, used as ahb input */

	}

};