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Commit f091f1d6 authored by Ingo Molnar's avatar Ingo Molnar Committed by Arnaldo Carvalho de Melo
Browse files

tools/headers: Synchronize kernel ABI headers, v4.16-rc1 



Sync the following tooling headers with the latest kernel version:

  tools/arch/powerpc/include/uapi/asm/kvm.h
  tools/arch/x86/include/asm/cpufeatures.h
  tools/include/uapi/drm/i915_drm.h
  tools/include/uapi/linux/if_link.h
  tools/include/uapi/linux/kvm.h

All the changes are new ABI additions which don't impact their use
in existing tooling.

Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 7a924536

tools/arch/powerpc/include/uapi/asm/kvm.h

+2 −0
Original line number Diff line number Diff line
@@ -632,6 +632,8 @@ struct kvm_ppc_cpu_char { 
#define KVM_REG_PPC_TIDR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)

#define KVM_REG_PPC_PSSCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)



#define KVM_REG_PPC_DEC_EXPIRY	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)



/* Transactional Memory checkpointed state:

 * This is all GPRs, all VSX regs and a subset of SPRs

 */

tools/arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -210,6 +210,7 @@ 


#define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */

#define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* "" Fill RSB on context switches */

#define X86_FEATURE_SEV			( 7*32+20) /* AMD Secure Encrypted Virtualization */



#define X86_FEATURE_USE_IBPB		( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */

tools/include/uapi/drm/i915_drm.h

+77 −0
Original line number Diff line number Diff line
@@ -86,6 +86,62 @@ enum i915_mocs_table_index { 
	I915_MOCS_CACHED,

};



/*

 * Different engines serve different roles, and there may be more than one

 * engine serving each role. enum drm_i915_gem_engine_class provides a

 * classification of the role of the engine, which may be used when requesting

 * operations to be performed on a certain subset of engines, or for providing

 * information about that group.

 */

enum drm_i915_gem_engine_class {

	I915_ENGINE_CLASS_RENDER	= 0,

	I915_ENGINE_CLASS_COPY		= 1,

	I915_ENGINE_CLASS_VIDEO		= 2,

	I915_ENGINE_CLASS_VIDEO_ENHANCE	= 3,



	I915_ENGINE_CLASS_INVALID	= -1

};



/**

 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915

 *

 */



enum drm_i915_pmu_engine_sample {

	I915_SAMPLE_BUSY = 0,

	I915_SAMPLE_WAIT = 1,

	I915_SAMPLE_SEMA = 2

};



#define I915_PMU_SAMPLE_BITS (4)

#define I915_PMU_SAMPLE_MASK (0xf)

#define I915_PMU_SAMPLE_INSTANCE_BITS (8)

#define I915_PMU_CLASS_SHIFT \

	(I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)



#define __I915_PMU_ENGINE(class, instance, sample) \

	((class) << I915_PMU_CLASS_SHIFT | \

	(instance) << I915_PMU_SAMPLE_BITS | \

	(sample))



#define I915_PMU_ENGINE_BUSY(class, instance) \

	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)



#define I915_PMU_ENGINE_WAIT(class, instance) \

	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)



#define I915_PMU_ENGINE_SEMA(class, instance) \

	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)



#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))



#define I915_PMU_ACTUAL_FREQUENCY	__I915_PMU_OTHER(0)

#define I915_PMU_REQUESTED_FREQUENCY	__I915_PMU_OTHER(1)

#define I915_PMU_INTERRUPTS		__I915_PMU_OTHER(2)

#define I915_PMU_RC6_RESIDENCY		__I915_PMU_OTHER(3)



#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY



/* Each region is a minimum of 16k, and there are at most 255 of them.

 */

#define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
@@ -450,6 +506,27 @@ typedef struct drm_i915_irq_wait { 
 */

#define I915_PARAM_HAS_EXEC_FENCE_ARRAY  49



/*

 * Query whether every context (both per-file default and user created) is

 * isolated (insofar as HW supports). If this parameter is not true, then

 * freshly created contexts may inherit values from an existing context,

 * rather than default HW values. If true, it also ensures (insofar as HW

 * supports) that all state set by this context will not leak to any other

 * context.

 *

 * As not every engine across every gen support contexts, the returned

 * value reports the support of context isolation for individual engines by

 * returning a bitmask of each engine class set to true if that class supports

 * isolation.

 */

#define I915_PARAM_HAS_CONTEXT_ISOLATION 50



/* Frequency of the command streamer timestamps given by the *_TIMESTAMP

 * registers. This used to be fixed per platform but from CNL onwards, this

 * might vary depending on the parts.

 */

#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51



typedef struct drm_i915_getparam {

	__s32 param;

	/*

tools/include/uapi/linux/if_link.h

+1 −0
Original line number Diff line number Diff line
@@ -163,6 +163,7 @@ enum { 
	IFLA_IF_NETNSID,

	IFLA_CARRIER_UP_COUNT,

	IFLA_CARRIER_DOWN_COUNT,

	IFLA_NEW_IFINDEX,

	__IFLA_MAX

};

tools/include/uapi/linux/kvm.h

+90 −0
Original line number Diff line number Diff line
@@ -1362,6 +1362,96 @@ struct kvm_s390_ucas_mapping { 
/* Available with KVM_CAP_S390_CMMA_MIGRATION */

#define KVM_S390_GET_CMMA_BITS      _IOWR(KVMIO, 0xb8, struct kvm_s390_cmma_log)

#define KVM_S390_SET_CMMA_BITS      _IOW(KVMIO, 0xb9, struct kvm_s390_cmma_log)

/* Memory Encryption Commands */

#define KVM_MEMORY_ENCRYPT_OP      _IOWR(KVMIO, 0xba, unsigned long)



struct kvm_enc_region {

	__u64 addr;

	__u64 size;

};



#define KVM_MEMORY_ENCRYPT_REG_REGION    _IOR(KVMIO, 0xbb, struct kvm_enc_region)

#define KVM_MEMORY_ENCRYPT_UNREG_REGION  _IOR(KVMIO, 0xbc, struct kvm_enc_region)



/* Secure Encrypted Virtualization command */

enum sev_cmd_id {

	/* Guest initialization commands */

	KVM_SEV_INIT = 0,

	KVM_SEV_ES_INIT,

	/* Guest launch commands */

	KVM_SEV_LAUNCH_START,

	KVM_SEV_LAUNCH_UPDATE_DATA,

	KVM_SEV_LAUNCH_UPDATE_VMSA,

	KVM_SEV_LAUNCH_SECRET,

	KVM_SEV_LAUNCH_MEASURE,

	KVM_SEV_LAUNCH_FINISH,

	/* Guest migration commands (outgoing) */

	KVM_SEV_SEND_START,

	KVM_SEV_SEND_UPDATE_DATA,

	KVM_SEV_SEND_UPDATE_VMSA,

	KVM_SEV_SEND_FINISH,

	/* Guest migration commands (incoming) */

	KVM_SEV_RECEIVE_START,

	KVM_SEV_RECEIVE_UPDATE_DATA,

	KVM_SEV_RECEIVE_UPDATE_VMSA,

	KVM_SEV_RECEIVE_FINISH,

	/* Guest status and debug commands */

	KVM_SEV_GUEST_STATUS,

	KVM_SEV_DBG_DECRYPT,

	KVM_SEV_DBG_ENCRYPT,

	/* Guest certificates commands */

	KVM_SEV_CERT_EXPORT,



	KVM_SEV_NR_MAX,

};



struct kvm_sev_cmd {

	__u32 id;

	__u64 data;

	__u32 error;

	__u32 sev_fd;

};



struct kvm_sev_launch_start {

	__u32 handle;

	__u32 policy;

	__u64 dh_uaddr;

	__u32 dh_len;

	__u64 session_uaddr;

	__u32 session_len;

};



struct kvm_sev_launch_update_data {

	__u64 uaddr;

	__u32 len;

};





struct kvm_sev_launch_secret {

	__u64 hdr_uaddr;

	__u32 hdr_len;

	__u64 guest_uaddr;

	__u32 guest_len;

	__u64 trans_uaddr;

	__u32 trans_len;

};



struct kvm_sev_launch_measure {

	__u64 uaddr;

	__u32 len;

};



struct kvm_sev_guest_status {

	__u32 handle;

	__u32 policy;

	__u32 state;

};



struct kvm_sev_dbg {

	__u64 src_uaddr;

	__u64 dst_uaddr;

	__u32 len;

};



#define KVM_DEV_ASSIGN_ENABLE_IOMMU	(1 << 0)

#define KVM_DEV_ASSIGN_PCI_2_3		(1 << 1)