Loading Documentation/cpusets.txt +1 −2 Original line number Diff line number Diff line Loading @@ -252,8 +252,7 @@ in a tasks processor placement. There is an exception to the above. If hotplug funtionality is used to remove all the CPUs that are currently assigned to a cpuset, then the kernel will automatically update the cpus_allowed of all tasks attached to CPUs in that cpuset with the online CPUs of the nearest parent cpuset that still has some CPUs online. When memory tasks attached to CPUs in that cpuset to allow all CPUs. When memory hotplug functionality for removing Memory Nodes is available, a similar exception is expected to apply there as well. In general, the kernel prefers to violate cpuset placement, over starving a task Loading Documentation/x86_64/boot-options.txt +3 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,9 @@ APICs noapictimer Don't set up the APIC timer no_timer_check Don't check the IO-APIC timer. This can work around problems with incorrect timer initialization on some boards. Early Console syntax: earlyprintk=vga Loading arch/i386/kernel/cpu/amd.c +6 −3 Original line number Diff line number Diff line Loading @@ -195,7 +195,7 @@ static void __init init_amd(struct cpuinfo_x86 *c) c->x86_num_cores = 1; } #ifdef CONFIG_X86_SMP #ifdef CONFIG_X86_HT /* * On a AMD dual core setup the lower bits of the APIC id * distingush the cores. Assumes number of cores is a power Loading @@ -203,8 +203,11 @@ static void __init init_amd(struct cpuinfo_x86 *c) */ if (c->x86_num_cores > 1) { int cpu = smp_processor_id(); /* Fix up the APIC ID following AMD specifications. */ cpu_core_id[cpu] >>= hweight32(c->x86_num_cores - 1); unsigned bits = 0; while ((1 << bits) < c->x86_num_cores) bits++; cpu_core_id[cpu] = phys_proc_id[cpu] & ((1<<bits)-1); phys_proc_id[cpu] >>= bits; printk(KERN_INFO "CPU %d(%d) -> Core %d\n", cpu, c->x86_num_cores, cpu_core_id[cpu]); } Loading arch/i386/kernel/cpu/common.c +1 −4 Original line number Diff line number Diff line Loading @@ -244,11 +244,8 @@ static void __init early_cpu_detect(void) early_intel_workaround(c); #ifdef CONFIG_SMP #ifdef CONFIG_X86_HT phys_proc_id[smp_processor_id()] = #endif cpu_core_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff; phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff; #endif } Loading arch/i386/kernel/smpboot.c +1 −0 Original line number Diff line number Diff line Loading @@ -888,6 +888,7 @@ void *xquad_portio; cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned; cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned; EXPORT_SYMBOL(cpu_core_map); static void __init smp_boot_cpus(unsigned int max_cpus) { Loading Loading
Documentation/cpusets.txt +1 −2 Original line number Diff line number Diff line Loading @@ -252,8 +252,7 @@ in a tasks processor placement. There is an exception to the above. If hotplug funtionality is used to remove all the CPUs that are currently assigned to a cpuset, then the kernel will automatically update the cpus_allowed of all tasks attached to CPUs in that cpuset with the online CPUs of the nearest parent cpuset that still has some CPUs online. When memory tasks attached to CPUs in that cpuset to allow all CPUs. When memory hotplug functionality for removing Memory Nodes is available, a similar exception is expected to apply there as well. In general, the kernel prefers to violate cpuset placement, over starving a task Loading
Documentation/x86_64/boot-options.txt +3 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,9 @@ APICs noapictimer Don't set up the APIC timer no_timer_check Don't check the IO-APIC timer. This can work around problems with incorrect timer initialization on some boards. Early Console syntax: earlyprintk=vga Loading
arch/i386/kernel/cpu/amd.c +6 −3 Original line number Diff line number Diff line Loading @@ -195,7 +195,7 @@ static void __init init_amd(struct cpuinfo_x86 *c) c->x86_num_cores = 1; } #ifdef CONFIG_X86_SMP #ifdef CONFIG_X86_HT /* * On a AMD dual core setup the lower bits of the APIC id * distingush the cores. Assumes number of cores is a power Loading @@ -203,8 +203,11 @@ static void __init init_amd(struct cpuinfo_x86 *c) */ if (c->x86_num_cores > 1) { int cpu = smp_processor_id(); /* Fix up the APIC ID following AMD specifications. */ cpu_core_id[cpu] >>= hweight32(c->x86_num_cores - 1); unsigned bits = 0; while ((1 << bits) < c->x86_num_cores) bits++; cpu_core_id[cpu] = phys_proc_id[cpu] & ((1<<bits)-1); phys_proc_id[cpu] >>= bits; printk(KERN_INFO "CPU %d(%d) -> Core %d\n", cpu, c->x86_num_cores, cpu_core_id[cpu]); } Loading
arch/i386/kernel/cpu/common.c +1 −4 Original line number Diff line number Diff line Loading @@ -244,11 +244,8 @@ static void __init early_cpu_detect(void) early_intel_workaround(c); #ifdef CONFIG_SMP #ifdef CONFIG_X86_HT phys_proc_id[smp_processor_id()] = #endif cpu_core_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff; phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff; #endif } Loading
arch/i386/kernel/smpboot.c +1 −0 Original line number Diff line number Diff line Loading @@ -888,6 +888,7 @@ void *xquad_portio; cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned; cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned; EXPORT_SYMBOL(cpu_core_map); static void __init smp_boot_cpus(unsigned int max_cpus) { Loading