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Commit efe53d8a authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/amdgpu: cleanup gfx_v9_0_init_queue() 



Introduce WREG32_FIELD15 macro for SOC15 architectures.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 714f88e0

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+3 −0
Original line number Diff line number Diff line
@@ -1704,6 +1704,9 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 
#define WREG32_FIELD_OFFSET(reg, offset, field, val)	\

	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))



#define WREG32_FIELD15(ip, idx, reg, field, val)	\

	WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))



/*

 * BIOS helpers.

 */

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −8
Original line number Diff line number Diff line
@@ -3975,9 +3975,7 @@ static int gfx_v9_0_init_queue(struct amdgpu_ring *ring) 
			       ring->pipe,

			       ring->queue, 0);

	/* disable wptr polling */

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));

	tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);

	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);



	/* write the EOP addr */

	BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
@@ -4121,11 +4119,8 @@ static int gfx_v9_0_init_queue(struct amdgpu_ring *ring) 
	amdgpu_bo_kunmap(ring->mqd_obj);

	amdgpu_bo_unreserve(ring->mqd_obj);



	if (use_doorbell) {

		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));

		tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);

	}

	if (use_doorbell)

		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);



	return 0;

}