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Commit ef2b56df authored by Nava kishore Manne's avatar Nava kishore Manne Committed by Greg Kroah-Hartman
Browse files

char: xilinx_hwicap: Fix kernel doc warnings 



This patch fixes the kernel doc warnings in the driver.

Signed-off-by: default avatarNava kishore Manne <navam@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 9f57ed09

drivers/char/xilinx_hwicap/xilinx_hwicap.c

+4 −0
Original line number Diff line number Diff line
@@ -222,6 +222,8 @@ static const struct config_registers v6_config_registers = { 
 * hwicap_command_desync - Send a DESYNC command to the ICAP port.

 * @drvdata: a pointer to the drvdata.

 *

 * Returns: '0' on success and failure value on error

 *

 * This command desynchronizes the ICAP After this command, a

 * bitstream containing a NULL packet, followed by a SYNCH packet is

 * required before the ICAP will recognize commands.
@@ -255,6 +257,8 @@ static int hwicap_command_desync(struct hwicap_drvdata *drvdata) 
 * 		Examples:  XHI_IDCODE, XHI_FLR.

 * @reg_data: returns the value of the register.

 *

 * Returns: '0' on success and failure value on error

 *

 * Sends a query packet to the ICAP and then receives the response.

 * The icap is left in Synched state.

 */

drivers/char/xilinx_hwicap/xilinx_hwicap.h

+5 −2
Original line number Diff line number Diff line
@@ -193,11 +193,12 @@ struct config_registers { 
 * hwicap_type_1_read - Generates a Type 1 read packet header.

 * @reg: is the address of the register to be read back.

 *

 * Return:

 * Generates a Type 1 read packet header, which is used to indirectly

 * read registers in the configuration logic.  This packet must then

 * be sent through the icap device, and a return packet received with

 * the information.

 **/

 */

static inline u32 hwicap_type_1_read(u32 reg)

{

	return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
@@ -208,7 +209,9 @@ static inline u32 hwicap_type_1_read(u32 reg) 
/**

 * hwicap_type_1_write - Generates a Type 1 write packet header

 * @reg: is the address of the register to be read back.

 **/

 *

 * Return: Type 1 write packet header

 */

static inline u32 hwicap_type_1_write(u32 reg)

{

	return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |