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Commit ee7bc638 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
Browse files

arm64: Set the safe value for L1 icache policy 



Right now we use 0 as the safe value for CTR_EL0:L1Ip, which is
not defined at the moment. The safer value for the L1Ip should be
the weakest of the policies, which happens to be AIVIVT. While at it,
fix the comment about safe_val.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 7ba5f605

arch/arm64/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ struct arm64_ftr_bits { 
	enum ftr_type	type;

	u8		shift;

	u8		width;

	s64		safe_val; /* safe value for discrete features */

	s64		safe_val; /* safe value for FTR_EXACT features */

};



/*

arch/arm64/kernel/cpufeature.c

+3 −2
Original line number Diff line number Diff line
@@ -150,9 +150,10 @@ static const struct arm64_ftr_bits ftr_ctr[] = { 
	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),	/* DminLine */

	/*

	 * Linux can handle differing I-cache policies. Userspace JITs will

	 * make use of *minLine

	 * make use of *minLine.

	 * If we have differing I-cache policies, report it as the weakest - AIVIVT.

	 */

	ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),	/* L1Ip */

	ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_AIVIVT),	/* L1Ip */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),	/* RAZ */

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),	/* IminLine */

	ARM64_FTR_END,