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Commit ede00740 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Add HaswellX V17 event file 



Add a Intel event file for perf.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-ungwt9avwpysik3yd1a06kpx@git.kernel.org


[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent dcfbad10

tools/perf/pmu-events/arch/x86/haswellx/cache.json

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tools/perf/pmu-events/arch/x86/haswellx/floating-point.json

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[

    {

        "EventCode": "0xC1",

        "UMask": "0x8",

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "Counter": "0,1,2,3",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "Errata": "HSD56, HSM57",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC1",

        "UMask": "0x10",

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "Counter": "0,1,2,3",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "Errata": "HSD56, HSM57",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x2",

        "BriefDescription": "Number of X87 assists due to output value.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "PublicDescription": "Number of X87 FP assists due to output values.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x4",

        "BriefDescription": "Number of X87 assists due to input value.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.X87_INPUT",

        "PublicDescription": "Number of X87 FP assists due to input values.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x8",

        "BriefDescription": "Number of SIMD FP assists due to Output values",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "PublicDescription": "Number of SIMD FP assists due to output values.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x10",

        "BriefDescription": "Number of SIMD FP assists due to input values",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "PublicDescription": "Number of SIMD FP assists due to input values.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x1e",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.ANY",

        "CounterMask": "1",

        "PublicDescription": "Cycles with any input/output SSE* or FP assists.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xC6",

        "UMask": "0x7",

        "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",

        "Counter": "0,1,2,3",

        "EventName": "AVX_INSTS.ALL",

        "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    }

]
 
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tools/perf/pmu-events/arch/x86/haswellx/frontend.json

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[

    {

        "EventCode": "0x79",

        "UMask": "0x2",

        "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.EMPTY",

        "Errata": "HSD135",

        "PublicDescription": "Counts cycles the IDQ is empty.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x4",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MITE_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x8",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.DSB_UOPS",

        "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x10",

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MS_DSB_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x20",

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MS_MITE_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x30",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MS_UOPS",

        "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x30",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MS_CYCLES",

        "CounterMask": "1",

        "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x4",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MITE_CYCLES",

        "CounterMask": "1",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x8",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.DSB_CYCLES",

        "CounterMask": "1",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x10",

        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MS_DSB_CYCLES",

        "CounterMask": "1",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EdgeDetect": "1",

        "EventCode": "0x79",

        "UMask": "0x10",

        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MS_DSB_OCCUR",

        "CounterMask": "1",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x18",

        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

        "CounterMask": "4",

        "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x18",

        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",

        "CounterMask": "1",

        "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x24",

        "BriefDescription": "Cycles MITE is delivering 4 Uops",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",

        "CounterMask": "4",

        "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x24",

        "BriefDescription": "Cycles MITE is delivering any Uop",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",

        "CounterMask": "1",

        "PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x79",

        "UMask": "0x3c",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MITE_ALL_UOPS",

        "PublicDescription": "Number of uops delivered to IDQ from any path.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x80",

        "UMask": "0x1",

        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",

        "Counter": "0,1,2,3",

        "EventName": "ICACHE.HIT",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x80",

        "UMask": "0x2",

        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",

        "Counter": "0,1,2,3",

        "EventName": "ICACHE.MISSES",

        "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",

        "SampleAfterValue": "200003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x80",

        "UMask": "0x4",

        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

        "Counter": "0,1,2,3",

        "EventName": "ICACHE.IFETCH_STALL",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x9C",

        "UMask": "0x1",

        "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",

        "Counter": "0,1,2,3",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

        "Errata": "HSD135",

        "PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0x9C",

        "UMask": "0x1",

        "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

        "Counter": "0,1,2,3",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

        "CounterMask": "4",

        "Errata": "HSD135",

        "PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled.  This event is counted on a per-core basis.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0x9C",

        "UMask": "0x1",

        "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",

        "Counter": "0,1,2,3",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",

        "CounterMask": "3",

        "Errata": "HSD135",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0x9C",

        "UMask": "0x1",

        "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

        "Counter": "0,1,2,3",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",

        "CounterMask": "2",

        "Errata": "HSD135",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0x9C",

        "UMask": "0x1",

        "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

        "Counter": "0,1,2,3",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

        "CounterMask": "1",

        "Errata": "HSD135",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "Invert": "1",

        "EventCode": "0x9C",

        "UMask": "0x1",

        "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

        "Counter": "0,1,2,3",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

        "CounterMask": "1",

        "Errata": "HSD135",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xAB",

        "UMask": "0x2",

        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

        "Counter": "0,1,2,3",

        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EdgeDetect": "1",

        "EventCode": "0x79",

        "UMask": "0x30",

        "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",

        "Counter": "0,1,2,3",

        "EventName": "IDQ.MS_SWITCHES",

        "CounterMask": "1",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x80",

        "UMask": "0x4",

        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

        "Counter": "0,1,2,3",

        "EventName": "ICACHE.IFDATA_STALL",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    }

]
 
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tools/perf/pmu-events/arch/x86/haswellx/memory.json

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tools/perf/pmu-events/arch/x86/haswellx/other.json

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[

    {

        "EventCode": "0x5C",

        "UMask": "0x1",

        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

        "Counter": "0,1,2,3",

        "EventName": "CPL_CYCLES.RING0",

        "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x5C",

        "UMask": "0x2",

        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

        "Counter": "0,1,2,3",

        "EventName": "CPL_CYCLES.RING123",

        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EdgeDetect": "1",

        "EventCode": "0x5C",

        "UMask": "0x1",

        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",

        "Counter": "0,1,2,3",

        "EventName": "CPL_CYCLES.RING0_TRANS",

        "CounterMask": "1",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x63",

        "UMask": "0x1",

        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

        "Counter": "0,1,2,3",

        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",

        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    }

]
 
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