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Commit ed0f72f4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC udpates from Vineet Gupta:

 - updates for various platforms

 - boot log updates for upcoming HS48 family of cores (dual issue)

* tag 'arc-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: [plat-hsdk]: Add reset controller node to manage ethernet reset
  ARC: [plat-hsdk]: Temporary fix to set CPU frequency to 1GHz
  ARC: fix allnoconfig build warning
  ARCv2: boot log: identify HS48 cores (dual issue)
  ARC: boot log: decontaminate ARCv2 ISA_CONFIG register
  arc: remove redundant UTS_MACHINE define in arch/arc/Makefile
  ARC: [plat-eznps] Update platform maintainer as Noam left
  ARC: [plat-hsdk] use actual clk driver to manage cpu clk
  ARC: [*defconfig] Reenable soft lock-up detector
  ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency
  ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency
  ARC: [plat-axs103] Add temporary quirk to reset ethernet IP
parents eab26ad1 ab8eb7db

MAINTAINERS

+2 −1
Original line number Diff line number Diff line
@@ -5259,7 +5259,8 @@ S: Maintained 
F:	drivers/iommu/exynos-iommu.c



EZchip NPS platform support

M:	Noam Camus <noamc@ezchip.com>

M:	Elad Kanfi <eladkan@mellanox.com>

M:	Vineet Gupta <vgupta@synopsys.com>

S:	Supported

F:	arch/arc/plat-eznps

F:	arch/arc/boot/dts/eznps.dts

arch/arc/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ config ARC 
	select GENERIC_SMP_IDLE_THREAD

	select HAVE_ARCH_KGDB

	select HAVE_ARCH_TRACEHOOK

	select HAVE_FUTEX_CMPXCHG

	select HAVE_FUTEX_CMPXCHG if FUTEX

	select HAVE_IOREMAP_PROT

	select HAVE_KPROBES

	select HAVE_KRETPROBES

arch/arc/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -6,8 +6,6 @@ 
# published by the Free Software Foundation.

#



UTS_MACHINE := arc



ifeq ($(CROSS_COMPILE),)

ifndef CONFIG_CPU_BIG_ENDIAN

CROSS_COMPILE := arc-linux-

arch/arc/boot/dts/axs10x_mb.dtsi

+8 −1
Original line number Diff line number Diff line
@@ -44,7 +44,14 @@ 


			mmcclk: mmcclk {

				compatible = "fixed-clock";

				clock-frequency = <50000000>;

				/*

				 * DW sdio controller has external ciu clock divider

				 * controlled via register in SDIO IP. It divides

				 * sdio_ref_clk (which comes from CGU) by 16 for

				 * default. So default mmcclk clock (which comes

				 * to sdk_in) is 25000000 Hz.

				 */

				clock-frequency = <25000000>;

				#clock-cells = <0>;

			};

arch/arc/boot/dts/hsdk.dts

+29 −3
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
/dts-v1/;



#include <dt-bindings/net/ti-dp83867.h>

#include <dt-bindings/reset/snps,hsdk-reset.h>



/ {

	model = "snps,hsdk";
@@ -57,10 +58,10 @@ 
		};

	};



	core_clk: core-clk {

	input_clk: input-clk {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		clock-frequency = <500000000>;

		clock-frequency = <33333333>;

	};



	cpu_intc: cpu-interrupt-controller {
@@ -102,6 +103,19 @@ 


		ranges = <0x00000000 0xf0000000 0x10000000>;



		cgu_rst: reset-controller@8a0 {

			compatible = "snps,hsdk-reset";

			#reset-cells = <1>;

			reg = <0x8A0 0x4>, <0xFF0 0x4>;

		};



		core_clk: core-clk@0 {

			compatible = "snps,hsdk-core-pll-clock";

			reg = <0x00 0x10>, <0x14B8 0x4>;

			#clock-cells = <0>;

			clocks = <&input_clk>;

		};



		serial: serial@5000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x5000 0x100>;
@@ -120,7 +134,17 @@ 


		mmcclk_ciu: mmcclk-ciu {

			compatible = "fixed-clock";

			clock-frequency = <100000000>;

			/*

			 * DW sdio controller has external ciu clock divider

			 * controlled via register in SDIO IP. Due to its

			 * unexpected default value (it should devide by 1

			 * but it devides by 8) SDIO IP uses wrong clock and

			 * works unstable (see STAR 9001204800)

			 * So add temporary fix and change clock frequency

			 * from 100000000 to 12500000 Hz until we fix dw sdio

			 * driver itself.

			 */

			clock-frequency = <12500000>;

			#clock-cells = <0>;

		};
@@ -141,6 +165,8 @@ 
			clocks = <&gmacclk>;

			clock-names = "stmmaceth";

			phy-handle = <&phy0>;

			resets = <&cgu_rst HSDK_ETH_RESET>;

			reset-names = "stmmaceth";



			mdio {

				#address-cells = <1>;