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Commit ece509c1 authored by Dylan Reid's avatar Dylan Reid Committed by Mark Brown
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ASoC: max98090: Correct pclk divisor settings 



The Baytrail-based chromebooks have a 20MHz mclk, the code was setting
the divisor incorrectly in this case.  According to the 98090
datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20.
Correct this and the surrounding clock ranges as well to match the
datasheet.

Signed-off-by: default avatarDylan Reid <dgreid@chromium.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f114040e

sound/soc/codecs/max98090.c

+3 −3
Original line number Diff line number Diff line
@@ -1941,13 +1941,13 @@ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 
	 *		 0x02 (when master clk is 20MHz to 40MHz)..

	 *		 0x03 (when master clk is 40MHz to 60MHz)..

	 */

	if ((freq >= 10000000) && (freq < 20000000)) {

	if ((freq >= 10000000) && (freq <= 20000000)) {

		snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,

			M98090_PSCLK_DIV1);

	} else if ((freq >= 20000000) && (freq < 40000000)) {

	} else if ((freq > 20000000) && (freq <= 40000000)) {

		snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,

			M98090_PSCLK_DIV2);

	} else if ((freq >= 40000000) && (freq < 60000000)) {

	} else if ((freq > 40000000) && (freq <= 60000000)) {

		snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,

			M98090_PSCLK_DIV4);

	} else {