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Commit ec71a398 authored by Kan Liang's avatar Kan Liang Committed by Ingo Molnar
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perf/x86/intel/ds: Handle PEBS overflow for fixed counters 



The pebs_drain() need to support fixed counters. The DS Save Area now
include "counter reset value" fields for each fixed counters.

Extend the related variables (e.g. mask, counters, error) to support
fixed counters. There is no extended PEBS in PEBS v2 and earlier PEBS
format. Only need to change the code for PEBS v3 and later PEBS format.

Extend the pebs_event_reset[] logic to support new "counter reset value" fields.

Increase the reserve space for fixed counters.

Based-on-code-from: Andi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: acme@kernel.org
Link: http://lkml.kernel.org/r/20180309021542.11374-3-kan.liang@linux.intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 4f08b625

arch/x86/events/intel/core.c

+4 −1
Original line number Diff line number Diff line
@@ -2282,6 +2282,9 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) 
	 * counters from the GLOBAL_STATUS mask and we always process PEBS

	 * events via drain_pebs().

	 */

	if (x86_pmu.flags & PMU_FL_PEBS_ALL)

		status &= ~cpuc->pebs_enabled;

	else

		status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);



	/*

arch/x86/events/intel/ds.c

+27 −9
Original line number Diff line number Diff line
@@ -903,10 +903,16 @@ static inline void pebs_update_threshold(struct cpu_hw_events *cpuc) 
{

	struct debug_store *ds = cpuc->ds;

	u64 threshold;

	int reserved;



	if (x86_pmu.flags & PMU_FL_PEBS_ALL)

		reserved = x86_pmu.max_pebs_events + x86_pmu.num_counters_fixed;

	else

		reserved = x86_pmu.max_pebs_events;



	if (cpuc->n_pebs == cpuc->n_large_pebs) {

		threshold = ds->pebs_absolute_maximum -

			x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;

			reserved * x86_pmu.pebs_record_size;

	} else {

		threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;

	}
@@ -970,7 +976,11 @@ void intel_pmu_pebs_enable(struct perf_event *event) 
	 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.

	 */

	if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {

		ds->pebs_event_reset[hwc->idx] =

		unsigned int idx = hwc->idx;



		if (idx >= INTEL_PMC_IDX_FIXED)

			idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);

		ds->pebs_event_reset[idx] =

			(u64)(-hwc->sample_period) & x86_pmu.cntval_mask;

	} else {

		ds->pebs_event_reset[hwc->idx] = 0;
@@ -1488,9 +1498,10 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) 
	struct debug_store *ds = cpuc->ds;

	struct perf_event *event;

	void *base, *at, *top;

	short counts[MAX_PEBS_EVENTS] = {};

	short error[MAX_PEBS_EVENTS] = {};

	int bit, i;

	short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

	short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

	int bit, i, size;

	u64 mask;



	if (!x86_pmu.pebs_active)

		return;
@@ -1500,6 +1511,13 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) 


	ds->pebs_index = ds->pebs_buffer_base;



	mask = (1ULL << x86_pmu.max_pebs_events) - 1;

	size = x86_pmu.max_pebs_events;

	if (x86_pmu.flags & PMU_FL_PEBS_ALL) {

		mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED;

		size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;

	}



	if (unlikely(base >= top)) {

		/*

		 * The drain_pebs() could be called twice in a short period
@@ -1509,7 +1527,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) 
		 * update the event->count for this case.

		 */

		for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled,

				 x86_pmu.max_pebs_events) {

				 size) {

			event = cpuc->events[bit];

			if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)

				intel_pmu_save_and_restart_reload(event, 0);
@@ -1522,12 +1540,12 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) 
		u64 pebs_status;



		pebs_status = p->status & cpuc->pebs_enabled;

		pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;

		pebs_status &= mask;



		/* PEBS v3 has more accurate status bits */

		if (x86_pmu.intel_cap.pebs_format >= 3) {

			for_each_set_bit(bit, (unsigned long *)&pebs_status,

					 x86_pmu.max_pebs_events)

					 size)

				counts[bit]++;



			continue;
@@ -1575,7 +1593,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) 
		counts[bit]++;

	}



	for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {

	for (bit = 0; bit < size; bit++) {

		if ((counts[bit] == 0) && (error[bit] == 0))

			continue;

arch/x86/include/asm/intel_ds.h

+2 −1
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 


/* The maximal number of PEBS events: */

#define MAX_PEBS_EVENTS		8

#define MAX_FIXED_PEBS_EVENTS	3



/*

 * A debug store configuration.
@@ -23,7 +24,7 @@ struct debug_store { 
	u64	pebs_index;

	u64	pebs_absolute_maximum;

	u64	pebs_interrupt_threshold;

	u64	pebs_event_reset[MAX_PEBS_EVENTS];

	u64	pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS];

} __aligned(PAGE_SIZE);



DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);