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Commit ebeac380 authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Jani Nikula
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drm/i915/glk: Validate only DSI PORT A PLL divider 



As per BSPEC, GLK supports MIPI DSI 8X clk only on PORT A.
Therefore only for PORT A PLL divider value should be validated.

Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1487335415-14766-8-git-send-email-madhav.chauhan@intel.com
parent bcc65700

drivers/gpu/drm/i915/intel_dsi_pll.c

+13 −6
Original line number Diff line number Diff line
@@ -206,18 +206,25 @@ static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) 
		return false;



	/*

	 * Both dividers must be programmed with valid values even if only one

	 * of the PLL is used, see BSpec/Broxton Clocks. Check this here for

	 * Dividers must be programmed with valid values. As per BSEPC, for

	 * GEMINLAKE only PORT A divider values are checked while for BXT

	 * both divider values are validated. Check this here for

	 * paranoia, since BIOS is known to misconfigure PLLs in this way at

	 * times, and since accessing DSI registers with invalid dividers

	 * causes a system hang.

	 */

	val = I915_READ(BXT_DSI_PLL_CTL);

	if (IS_GEMINILAKE(dev_priv)) {

		if (!(val & BXT_DSIA_16X_MASK)) {

			DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);

			enabled = false;

		}

	} else {

		if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {

		DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n",

				 val);

			DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);

			enabled = false;

		}

	}



	return enabled;

}