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Commit eb3d3ec5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into next 

Pull ARM updates from Russell King:

 - Major clean-up of the L2 cache support code.  The existing mess was
   becoming rather unmaintainable through all the additions that others
   have done over time.  This turns it into a much nicer structure, and
   implements a few performance improvements as well.

 - Clean up some of the CP15 control register tweaks for alignment
   support, moving some code and data into alignment.c

 - DMA properties for ARM, from Santosh and reviewed by DT people.  This
   adds DT properties to specify bus translations we can't discover
   automatically, and to indicate whether devices are coherent.

 - Hibernation support for ARM

 - Make ftrace work with read-only text in modules

 - add suspend support for PJ4B CPUs

 - rework interrupt masking for undefined instruction handling, which
   allows us to enable interrupts earlier in the handling of these
   exceptions.

 - support for big endian page tables

 - fix stacktrace support to exclude stacktrace functions from the
   trace, and add save_stack_trace_regs() implementation so that kprobes
   can record stack traces.

 - Add support for the Cortex-A17 CPU.

 - Remove last vestiges of ARM710 support.

 - Removal of ARM "meminfo" structure, finally converting us solely to
   memblock to handle the early memory initialisation.

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits)
  ARM: ensure C page table setup code follows assembly code (part II)
  ARM: ensure C page table setup code follows assembly code
  ARM: consolidate last remaining open-coded alignment trap enable
  ARM: remove global cr_no_alignment
  ARM: remove CPU_CP15 conditional from alignment.c
  ARM: remove unused adjust_cr() function
  ARM: move "noalign" command line option to alignment.c
  ARM: provide common method to clear bits in CPU control register
  ARM: 8025/1: Get rid of meminfo
  ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type
  ARM: 8066/1: correction for ARM patch 8031/2
  ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation
  ARM: 8065/1: remove last use of CONFIG_CPU_ARM710
  ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction
  ARM: 8047/1: rwsem: use asm-generic rwsem implementation
  ARM: l2c: trial at enabling some Cortex-A9 optimisations
  ARM: l2c: add warnings for stuff modifying aux_ctrl register values
  ARM: l2c: print a warning with L2C-310 caches if the cache size is modified
  ARM: l2c: remove old .set_debug method
  ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this
  ...
parents c3c55a07 bd63ce27

Documentation/arm/memory.txt

+1 −8
Original line number Diff line number Diff line
@@ -41,16 +41,9 @@ fffe8000 fffeffff DTCM mapping area for platforms with 
fffe0000	fffe7fff	ITCM mapping area for platforms with

				ITCM mounted inside the CPU.



fff00000	fffdffff	Fixmap mapping region.  Addresses provided

ffc00000	ffdfffff	Fixmap mapping region.  Addresses provided

				by fix_to_virt() will be located here.



ffc00000	ffefffff	DMA memory mapping region.  Memory returned

				by the dma_alloc_xxx functions will be

				dynamically mapped here.



ff000000	ffbfffff	Reserved for future expansion of DMA

				mapping region.



fee00000	feffffff	Mapping of PCI I/O space. This is a static

				mapping within the vmalloc space.

Documentation/devicetree/bindings/arm/pmu.txt

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required properties: 


- compatible : should be one of

	"arm,armv8-pmuv3"

	"arm,cortex-a17-pmu"

	"arm,cortex-a15-pmu"

	"arm,cortex-a12-pmu"

	"arm,cortex-a9-pmu"

arch/arm/Kconfig

+6 −60
Original line number Diff line number Diff line
@@ -165,12 +165,9 @@ config TRACE_IRQFLAGS_SUPPORT 
	bool

	default y



config RWSEM_GENERIC_SPINLOCK

	bool

	default y



config RWSEM_XCHGADD_ALGORITHM

	bool

	default y



config ARCH_HAS_ILOG2_U32

	bool
@@ -1089,11 +1086,6 @@ source "arch/arm/firmware/Kconfig" 


source arch/arm/mm/Kconfig



config ARM_NR_BANKS

	int

	default 16 if ARCH_EP93XX

	default 8



config IWMMXT

	bool "Enable iWMMXt support"

	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
@@ -1214,19 +1206,6 @@ config ARM_ERRATA_742231 
	  register of the Cortex-A9 which reduces the linefill issuing

	  capabilities of the processor.



config PL310_ERRATA_588369

	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"

	depends on CACHE_L2X0

	help

	   The PL310 L2 cache controller implements three types of Clean &

	   Invalidate maintenance operations: by Physical Address

	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).

	   They are architecturally defined to behave as the execution of a

	   clean operation followed immediately by an invalidate operation,

	   both performing to the same memory location. This functionality

	   is not correctly implemented in PL310 as clean lines are not

	   invalidated as a result of these operations.



config ARM_ERRATA_643719

	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"

	depends on CPU_V7 && SMP
@@ -1249,17 +1228,6 @@ config ARM_ERRATA_720789 
	  tables. The workaround changes the TLB flushing routines to invalidate

	  entries regardless of the ASID.



config PL310_ERRATA_727915

	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"

	depends on CACHE_L2X0

	help

	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance

	  operation (offset 0x7FC). This operation runs in background so that

	  PL310 can handle normal accesses while it is in progress. Under very

	  rare circumstances, due to this erratum, write data can be lost when

	  PL310 treats a cacheable write transaction during a Clean &

	  Invalidate by Way operation.



config ARM_ERRATA_743622

	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"

	depends on CPU_V7
@@ -1285,21 +1253,6 @@ config ARM_ERRATA_751472 
	  operation is received by a CPU before the ICIALLUIS has completed,

	  potentially leading to corrupted entries in the cache or TLB.



config PL310_ERRATA_753970

	bool "PL310 errata: cache sync operation may be faulty"

	depends on CACHE_PL310

	help

	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.



	  Under some condition the effect of cache sync operation on

	  the store buffer still remains when the operation completes.

	  This means that the store buffer is always asked to drain and

	  this prevents it from merging any further writes. The workaround

	  is to replace the normal offset of cache sync operation (0x730)

	  by another offset targeting an unmapped PL310 register 0x740.

	  This has the same effect as the cache sync operation: store buffer

	  drain and waiting for all buffers empty.



config ARM_ERRATA_754322

	bool "ARM errata: possible faulty MMU translations following an ASID switch"

	depends on CPU_V7
@@ -1348,18 +1301,6 @@ config ARM_ERRATA_764369 
	  relevant cache maintenance functions and sets a specific bit

	  in the diagnostic control register of the SCU.



config PL310_ERRATA_769419

	bool "PL310 errata: no automatic Store Buffer drain"

	depends on CACHE_L2X0

	help

	  On revisions of the PL310 prior to r3p2, the Store Buffer does

	  not automatically drain. This can cause normal, non-cacheable

	  writes to be retained when the memory system is idle, leading

	  to suboptimal I/O performance for drivers using coherent DMA.

	  This option adds a write barrier to the cpu_idle loop so that,

	  on systems with an outer cache, the store buffer is drained

	  explicitly.



config ARM_ERRATA_775420

       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"

       depends on CPU_V7
@@ -2279,6 +2220,11 @@ config ARCH_SUSPEND_POSSIBLE 
config ARM_CPU_SUSPEND

	def_bool PM_SLEEP



config ARCH_HIBERNATION_POSSIBLE

	bool

	depends on MMU

	default y if ARCH_SUSPEND_POSSIBLE



endmenu



source "net/Kconfig"

arch/arm/boot/compressed/atags_to_fdt.c

+2 −0
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 
#define do_extend_cmdline 0

#endif



#define NR_BANKS 16



static int node_offset(void *fdt, const char *node_path)

{

	int offset = fdt_path_offset(fdt, node_path);

arch/arm/boot/dts/marco.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
		ranges = <0x40000000 0x40000000 0xa0000000>;



		l2-cache-controller@c0030000 {

			compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";

			compatible = "arm,pl310-cache";

			reg = <0xc0030000 0x1000>;

			interrupts = <0 59 0>;

			arm,tag-latency = <1 1 1>;