Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ea9c7405 authored by Niklas Söderlund's avatar Niklas Söderlund Committed by Geert Uytterhoeven
Browse files

pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength 



There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
drive-strength to be configured. Add those pins to the list of pins and
to the drive-strength configuration registers.

The pins can now be referred to in DT by function names and their
drive-strength modified.

Signed-off-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 1ce56aea

drivers/pinctrl/sh-pfc/pfc-r8a7795.c

+148 −15
Original line number Diff line number Diff line
@@ -523,6 +523,22 @@ MOD_SEL0_2_1 MOD_SEL1_2 \ 
			MOD_SEL1_1 \

			MOD_SEL1_0		MOD_SEL2_0



/*

 * These pins are not able to be muxed but have other properties

 * that can be set, such as drive-strength or pull-up/pull-down enable.

 */

#define PINMUX_STATIC \

	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \

	FM(QSPI0_IO2) FM(QSPI0_IO3) \

	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \

	FM(QSPI1_IO2) FM(QSPI1_IO3) \

	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \

	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \

	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \

	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \

	FM(CLKOUT) FM(PRESETOUT) \

	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \

	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF)



enum {

	PINMUX_RESERVED = 0,
@@ -548,6 +564,7 @@ enum { 
	PINMUX_GPSR

	PINMUX_IPSR

	PINMUX_MOD_SELS

	PINMUX_STATIC

	PINMUX_MARK_END,

#undef F_

#undef FM
@@ -1412,10 +1429,78 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP17_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),

	PINMUX_IPSR_MSEL(IP17_7_4,	RIF2_D1_B,		SEL_DRIF2_1),

	PINMUX_IPSR_GPSR(IP17_7_4,	TPU0TO3),



/*

 * Static pins can not be muxed between different functions but

 * still needs a mark entry in the pinmux list. Add each static

 * pin to the list without an associated function. The sh-pfc

 * core will do the right thing and skip trying to mux then pin

 * while still applying configuration to it

 */

#define FM(x)	PINMUX_DATA(x##_MARK, 0),

	PINMUX_STATIC

#undef FM

};



/*

 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.

 * Physical layout rows: A - AW, cols: 1 - 39.

 */

#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))

#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)

#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)



static const struct sh_pfc_pin pinmux_pins[] = {

	PINMUX_GPIO_GP_ALL(),



	/*

	 * Pins not associated with a GPIO port.

	 *

	 * The pin positions are different between different r8a7795

	 * packages, all that is needed for the pfc driver is a unique

	 * number for each pin. To this end use the pin layout from

	 * R-Car H3SiP to calculate a unique number for each pin.

	 */

	SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('F',  1, CLKOUT, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  7, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

	SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),

};



/* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -4962,7 +5047,42 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
};



static const struct pinmux_drive_reg pinmux_drive_regs[] = {

	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {

		{ PIN_NUMBER('W', 3),   28, 2 },	/* QSPI0_SPCLK */

		{ PIN_A_NUMBER('C', 5), 24, 2 },	/* QSPI0_MOSI_IO0 */

		{ PIN_A_NUMBER('B', 4), 20, 2 },	/* QSPI0_MISO_IO1 */

		{ PIN_NUMBER('Y', 6),   16, 2 },	/* QSPI0_IO2 */

		{ PIN_A_NUMBER('B', 6), 12, 2 },	/* QSPI0_IO3 */

		{ PIN_NUMBER('Y', 3),    8, 2 },	/* QSPI0_SSL */

		{ PIN_NUMBER('V', 3),    4, 2 },	/* QSPI1_SPCLK */

		{ PIN_A_NUMBER('C', 7),  0, 2 },	/* QSPI1_MOSI_IO0 */

	} },

	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {

		{ PIN_A_NUMBER('E', 5), 28, 2 },	/* QSPI1_MISO_IO1 */

		{ PIN_A_NUMBER('E', 4), 24, 2 },	/* QSPI1_IO2 */

		{ PIN_A_NUMBER('C', 3), 20, 2 },	/* QSPI1_IO3 */

		{ PIN_NUMBER('V', 5),   16, 2 },	/* QSPI1_SSL */

		{ PIN_NUMBER('Y', 7),   12, 2 },	/* RPC_INT# */

		{ PIN_NUMBER('V', 6),    8, 2 },	/* RPC_WP# */

		{ PIN_NUMBER('V', 7),    4, 2 },	/* RPC_RESET# */

		{ PIN_NUMBER('A', 16),   0, 3 },	/* AVB_RX_CTL */

	} },

	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {

		{ PIN_NUMBER('B', 19),  28, 3 },	/* AVB_RXC */

		{ PIN_NUMBER('A', 13),  24, 3 },	/* AVB_RD0 */

		{ PIN_NUMBER('B', 13),  20, 3 },	/* AVB_RD1 */

		{ PIN_NUMBER('A', 14),  16, 3 },	/* AVB_RD2 */

		{ PIN_NUMBER('B', 14),  12, 3 },	/* AVB_RD3 */

		{ PIN_NUMBER('A', 8),    8, 3 },	/* AVB_TX_CTL */

		{ PIN_NUMBER('A', 19),   4, 3 },	/* AVB_TXC */

		{ PIN_NUMBER('A', 18),   0, 3 },	/* AVB_TD0 */

	} },

	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {

		{ PIN_NUMBER('B', 18),  28, 3 },	/* AVB_TD1 */

		{ PIN_NUMBER('A', 17),  24, 3 },	/* AVB_TD2 */

		{ PIN_NUMBER('B', 17),  20, 3 },	/* AVB_TD3 */

		{ PIN_NUMBER('A', 12),  16, 3 },	/* AVB_TXCREFCLK */

		{ PIN_NUMBER('A', 9),   12, 3 },	/* AVB_MDIO */

		{ RCAR_GP_PIN(2,  9),    8, 3 },	/* AVB_MDC */

		{ RCAR_GP_PIN(2, 10),    4, 3 },	/* AVB_MAGIC */

		{ RCAR_GP_PIN(2, 11),    0, 3 },	/* AVB_PHY_INT */
@@ -5008,6 +5128,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { 
		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */

	} },

	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {

		{ PIN_NUMBER('F', 1), 28, 3 },	/* CLKOUT */

		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */

		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */

		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
@@ -5018,6 +5139,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { 
	} },

	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {

		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */

		{ PIN_NUMBER('C', 1), 24, 3 },	/* PRESETOUT# */

		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */

		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */

		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
@@ -5042,8 +5164,18 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { 
		{ RCAR_GP_PIN(7,  1),   16, 3 },	/* AVS2 */

		{ RCAR_GP_PIN(7,  2),   12, 3 },	/* HDMI0_CEC */

		{ RCAR_GP_PIN(7,  3),    8, 3 },	/* HDMI1_CEC */

		{ PIN_A_NUMBER('P', 7),  4, 2 },	/* DU_DOTCLKIN0 */

		{ PIN_A_NUMBER('P', 8),  0, 2 },	/* DU_DOTCLKIN1 */

	} },

	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {

		{ PIN_A_NUMBER('R', 7),  28, 2 },	/* DU_DOTCLKIN2 */

		{ PIN_A_NUMBER('R', 8),  24, 2 },	/* DU_DOTCLKIN3 */

		{ PIN_A_NUMBER('D', 38), 20, 2 },	/* FSCLKST# */

		{ PIN_A_NUMBER('R', 30),  4, 2 },	/* TMS */

	} },

	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {

		{ PIN_A_NUMBER('T', 28), 28, 2 },	/* TDO */

		{ PIN_A_NUMBER('T', 30), 24, 2 },	/* ASEBRK */

		{ RCAR_GP_PIN(3,  0),    20, 3 },	/* SD0_CLK */

		{ RCAR_GP_PIN(3,  1),    16, 3 },	/* SD0_CMD */

		{ RCAR_GP_PIN(3,  2),    12, 3 },	/* SD0_DAT0 */
@@ -5118,6 +5250,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { 
		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */

		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */

		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */

		{ PIN_NUMBER('H', 37),  4, 3 },	/* MLB_REF */

		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */

	} },

	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {