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Commit e9f9fe35 authored by Dinh Nguyen's avatar Dinh Nguyen
Browse files

ARM: socfpga: dts: Fix gpio dts entry for the correct clock 



The correct clock for the HPS gpio(s) should be the l4_mp_clk.

Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
parent c5dab6e2

arch/arm/boot/dts/socfpga.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -565,7 +565,7 @@ 
			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0xff708000 0x1000>;

			clocks = <&per_base_clk>;

			clocks = <&l4_mp_clk>;

			status = "disabled";



			porta: gpio-controller@0 {
@@ -585,7 +585,7 @@ 
			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0xff709000 0x1000>;

			clocks = <&per_base_clk>;

			clocks = <&l4_mp_clk>;

			status = "disabled";



			portb: gpio-controller@0 {
@@ -605,7 +605,7 @@ 
			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0xff70a000 0x1000>;

			clocks = <&per_base_clk>;

			clocks = <&l4_mp_clk>;

			status = "disabled";



			portc: gpio-controller@0 {