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Commit e8d85d76 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman
Browse files

ARM: dts: meson8b: add the cortex-a5-pmu compatible PMU



Enable the performance monitor unit on Meson8b.

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 17b66027
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+13 −4
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@200 {
		cpu0: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
@@ -64,7 +64,7 @@
			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
		};

		cpu@201 {
		cpu1: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
@@ -73,7 +73,7 @@
			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
		};

		cpu@202 {
		cpu2: cpu@202 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
@@ -82,7 +82,7 @@
			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
		};

		cpu@203 {
		cpu3: cpu@203 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
@@ -92,6 +92,15 @@
		};
	};

	pmu {
		compatible = "arm,cortex-a5-pmu";
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;