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Commit e8576e68 authored by Paul Zimmerman's avatar Paul Zimmerman Committed by Greg Kroah-Hartman
Browse files

staging: dwc2: move function to more logical place 



The function dwc2_get_hwparams() was in an awkward place, mixed
in with the dwc2_set_param* functions. Move it down after those
functions.

Signed-off-by: default avatarPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e7e59e11

drivers/staging/dwc2/core.c

+62 −62
Original line number Diff line number Diff line
@@ -2510,6 +2510,68 @@ void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) 
	hsotg->core_params->otg_ver = val;

}



void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)

{

	if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {

		if (val >= 0) {

			dev_err(hsotg->dev,

				"'%d' invalid for parameter uframe_sched\n",

				val);

			dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");

		}

		val = 1;

		dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);

	}



	hsotg->core_params->uframe_sched = val;

}



/*

 * This function is called during module intialization to pass module parameters

 * for the DWC_otg core.

 */

void dwc2_set_parameters(struct dwc2_hsotg *hsotg,

			 const struct dwc2_core_params *params)

{

	dev_dbg(hsotg->dev, "%s()\n", __func__);



	dwc2_set_param_otg_cap(hsotg, params->otg_cap);

	dwc2_set_param_dma_enable(hsotg, params->dma_enable);

	dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);

	dwc2_set_param_host_support_fs_ls_low_power(hsotg,

			params->host_support_fs_ls_low_power);

	dwc2_set_param_enable_dynamic_fifo(hsotg,

			params->enable_dynamic_fifo);

	dwc2_set_param_host_rx_fifo_size(hsotg,

			params->host_rx_fifo_size);

	dwc2_set_param_host_nperio_tx_fifo_size(hsotg,

			params->host_nperio_tx_fifo_size);

	dwc2_set_param_host_perio_tx_fifo_size(hsotg,

			params->host_perio_tx_fifo_size);

	dwc2_set_param_max_transfer_size(hsotg,

			params->max_transfer_size);

	dwc2_set_param_max_packet_count(hsotg,

			params->max_packet_count);

	dwc2_set_param_host_channels(hsotg, params->host_channels);

	dwc2_set_param_phy_type(hsotg, params->phy_type);

	dwc2_set_param_speed(hsotg, params->speed);

	dwc2_set_param_host_ls_low_power_phy_clk(hsotg,

			params->host_ls_low_power_phy_clk);

	dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);

	dwc2_set_param_phy_ulpi_ext_vbus(hsotg,

			params->phy_ulpi_ext_vbus);

	dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);

	dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);

	dwc2_set_param_ts_dline(hsotg, params->ts_dline);

	dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);

	dwc2_set_param_en_multiple_tx_fifo(hsotg,

			params->en_multiple_tx_fifo);

	dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);

	dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);

	dwc2_set_param_otg_ver(hsotg, params->otg_ver);

	dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);

}



/**

 * During device initialization, read various hardware configuration

 * registers and interpret the contents.
@@ -2669,68 +2731,6 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 
	return 0;

}



void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)

{

	if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {

		if (val >= 0) {

			dev_err(hsotg->dev,

				"'%d' invalid for parameter uframe_sched\n",

				val);

			dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");

		}

		val = 1;

		dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);

	}



	hsotg->core_params->uframe_sched = val;

}



/*

 * This function is called during module intialization to pass module parameters

 * for the DWC_otg core.

 */

void dwc2_set_parameters(struct dwc2_hsotg *hsotg,

			 const struct dwc2_core_params *params)

{

	dev_dbg(hsotg->dev, "%s()\n", __func__);



	dwc2_set_param_otg_cap(hsotg, params->otg_cap);

	dwc2_set_param_dma_enable(hsotg, params->dma_enable);

	dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);

	dwc2_set_param_host_support_fs_ls_low_power(hsotg,

			params->host_support_fs_ls_low_power);

	dwc2_set_param_enable_dynamic_fifo(hsotg,

			params->enable_dynamic_fifo);

	dwc2_set_param_host_rx_fifo_size(hsotg,

			params->host_rx_fifo_size);

	dwc2_set_param_host_nperio_tx_fifo_size(hsotg,

			params->host_nperio_tx_fifo_size);

	dwc2_set_param_host_perio_tx_fifo_size(hsotg,

			params->host_perio_tx_fifo_size);

	dwc2_set_param_max_transfer_size(hsotg,

			params->max_transfer_size);

	dwc2_set_param_max_packet_count(hsotg,

			params->max_packet_count);

	dwc2_set_param_host_channels(hsotg, params->host_channels);

	dwc2_set_param_phy_type(hsotg, params->phy_type);

	dwc2_set_param_speed(hsotg, params->speed);

	dwc2_set_param_host_ls_low_power_phy_clk(hsotg,

			params->host_ls_low_power_phy_clk);

	dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);

	dwc2_set_param_phy_ulpi_ext_vbus(hsotg,

			params->phy_ulpi_ext_vbus);

	dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);

	dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);

	dwc2_set_param_ts_dline(hsotg, params->ts_dline);

	dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);

	dwc2_set_param_en_multiple_tx_fifo(hsotg,

			params->en_multiple_tx_fifo);

	dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);

	dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);

	dwc2_set_param_otg_ver(hsotg, params->otg_ver);

	dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);

}



u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)

{

	return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;