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Commit e61cd5e2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm radeon fixes from Dave Airlie:
 "One core fix, but mostly radeon fixes for s/r and big endian UVD
  support, and a fix to stop the GPU being reset for no good reason, and
  crashing people's machines."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/radeon: update lockup tracking when scheduling in empty ring
  drm/prime: Honor requested file flags when exporting a buffer
  drm/radeon: fix UVD on big endian
  drm/radeon: fix write back suspend regression with uvd v2
  drm/radeon: do not try to uselessly update virtual memory pagetable
parents 64a2f30a 9aa36876

drivers/gpu/drm/drm_prime.c

+1 −2
Original line number Diff line number Diff line
@@ -190,8 +190,7 @@ struct dma_buf *drm_gem_prime_export(struct drm_device *dev, 
		if (ret)

			return ERR_PTR(ret);

	}

	return dma_buf_export(obj, &drm_gem_prime_dmabuf_ops, obj->size,

			      0600);

	return dma_buf_export(obj, &drm_gem_prime_dmabuf_ops, obj->size, flags);

}

EXPORT_SYMBOL(drm_gem_prime_export);

drivers/gpu/drm/radeon/r600.c

+10 −3
Original line number Diff line number Diff line
@@ -2687,6 +2687,9 @@ void r600_uvd_rbc_stop(struct radeon_device *rdev) 
int r600_uvd_init(struct radeon_device *rdev)

{

	int i, j, r;

	/* disable byte swapping */

	u32 lmi_swap_cntl = 0;

	u32 mp_swap_cntl = 0;



	/* raise clocks while booting up the VCPU */

	radeon_set_uvd_clocks(rdev, 53300, 40000);
@@ -2711,9 +2714,13 @@ int r600_uvd_init(struct radeon_device *rdev) 
	WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |

			     (1 << 21) | (1 << 9) | (1 << 20));



	/* disable byte swapping */

	WREG32(UVD_LMI_SWAP_CNTL, 0);

	WREG32(UVD_MP_SWAP_CNTL, 0);

#ifdef __BIG_ENDIAN

	/* swap (8 in 32) RB and IB */

	lmi_swap_cntl = 0xa;

	mp_swap_cntl = 0;

#endif

	WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);

	WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);



	WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);

	WREG32(UVD_MPC_SET_MUXA1, 0x0);

drivers/gpu/drm/radeon/radeon_device.c

+24 −29
Original line number Diff line number Diff line
@@ -244,16 +244,6 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 
 */

void radeon_wb_disable(struct radeon_device *rdev)

{

	int r;



	if (rdev->wb.wb_obj) {

		r = radeon_bo_reserve(rdev->wb.wb_obj, false);

		if (unlikely(r != 0))

			return;

		radeon_bo_kunmap(rdev->wb.wb_obj);

		radeon_bo_unpin(rdev->wb.wb_obj);

		radeon_bo_unreserve(rdev->wb.wb_obj);

	}

	rdev->wb.enabled = false;

}
@@ -269,6 +259,11 @@ void radeon_wb_fini(struct radeon_device *rdev) 
{

	radeon_wb_disable(rdev);

	if (rdev->wb.wb_obj) {

		if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {

			radeon_bo_kunmap(rdev->wb.wb_obj);

			radeon_bo_unpin(rdev->wb.wb_obj);

			radeon_bo_unreserve(rdev->wb.wb_obj);

		}

		radeon_bo_unref(&rdev->wb.wb_obj);

		rdev->wb.wb = NULL;

		rdev->wb.wb_obj = NULL;
@@ -295,7 +290,6 @@ int radeon_wb_init(struct radeon_device *rdev) 
			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);

			return r;

		}

	}

		r = radeon_bo_reserve(rdev->wb.wb_obj, false);

		if (unlikely(r != 0)) {

			radeon_wb_fini(rdev);
@@ -316,6 +310,7 @@ int radeon_wb_init(struct radeon_device *rdev) 
			radeon_wb_fini(rdev);

			return r;

		}

	}



	/* clear wb memory */

	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);

drivers/gpu/drm/radeon/radeon_fence.c

+8 −2
Original line number Diff line number Diff line
@@ -63,7 +63,9 @@ static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring) 
{

	struct radeon_fence_driver *drv = &rdev->fence_drv[ring];

	if (likely(rdev->wb.enabled || !drv->scratch_reg)) {

		if (drv->cpu_addr) {

			*drv->cpu_addr = cpu_to_le32(seq);

		}

	} else {

		WREG32(drv->scratch_reg, seq);

	}
@@ -84,7 +86,11 @@ static u32 radeon_fence_read(struct radeon_device *rdev, int ring) 
	u32 seq = 0;



	if (likely(rdev->wb.enabled || !drv->scratch_reg)) {

		if (drv->cpu_addr) {

			seq = le32_to_cpu(*drv->cpu_addr);

		} else {

			seq = lower_32_bits(atomic64_read(&drv->last_seq));

		}

	} else {

		seq = RREG32(drv->scratch_reg);

	}

drivers/gpu/drm/radeon/radeon_gart.c

+4 −2
Original line number Diff line number Diff line
@@ -1197,11 +1197,13 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev, 
int radeon_vm_bo_rmv(struct radeon_device *rdev,

		     struct radeon_bo_va *bo_va)

{

	int r;

	int r = 0;



	mutex_lock(&rdev->vm_manager.lock);

	mutex_lock(&bo_va->vm->mutex);

	if (bo_va->soffset) {

		r = radeon_vm_bo_update_pte(rdev, bo_va->vm, bo_va->bo, NULL);

	}

	mutex_unlock(&rdev->vm_manager.lock);

	list_del(&bo_va->vm_list);

	mutex_unlock(&bo_va->vm->mutex);