Commit e592f658 authored May 10, 2018 by Martin Blumenstingl Committed by Kevin Hilman May 10, 2018

ARM: dts: meson: add support for the Meson8m2 SoC



This adds a meson8m2.dtsi which simply inherits meson8.dtsi as both SoCs
share most peripherals.
The known differences are:
- Meson8m2's hardware video decoder additionally supports H.265 decoding
- Meson8m2 has the same Gigabit MAC as Meson8b (instead of the 10/100M
  MAC that Meson8 uses)
- Meson8m2 uses the same watchdog register layout/bits as Meson8b (using
  the Meson8 watchdog compatible leads to an infinite hang when
  rebooting the machine)
- Meson8m2 uses the same SAR ADC register layout/bits as Meson8b.
  However, it uses the temperature sensor calibration formula (and
  registers) Meson8b which differ from Meson8. This however is currently
  not supported by the meson-saradc driver yet.
- the pin controller is mostly compatible with Meson8, Meson8m2 has
  an additional function on eight pins and removes the "VGA" function.
  So there's a total of 10 pins which are slightly changed, which is why
  there's a separate compatible for the pin controller
- a separate compatible for the clock controller is used because at
  least the Mali clock tree (not supported yet) is the same as on GXBB
  while Meson8 and Meson8b have a reduced/older version of the Mali
  clock tree.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

parent 0633d20f

arch/arm/boot/dts/meson8m2.dtsi

0 → 100644

+54 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
		/*
		* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
		*/

		#include "meson8.dtsi"

		/ {
		model = "Amlogic Meson8m2 SoC";
		compatible = "amlogic,meson8m2";
		}; /* end of / */

		&clkc {
		compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
		};

		&ethmac {
		compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
		reg = <0xc9410000 0x10000
		0xc1108140 0x8>;
		clocks = <&clkc CLKID_ETH>,
		<&clkc CLKID_MPLL2>,
		<&clkc CLKID_MPLL2>;
		clock-names = "stmmaceth", "clkin0", "clkin1";
		resets = <&reset RESET_ETHERNET>;
		reset-names = "stmmaceth";
		};

		&pinctrl_aobus {
		compatible = "amlogic,meson8m2-aobus-pinctrl",
		"amlogic,meson8-aobus-pinctrl";
		};

		&pinctrl_cbus {
		compatible = "amlogic,meson8m2-cbus-pinctrl",
		"amlogic,meson8-cbus-pinctrl";

		eth_rgmii_pins: ethernet {
		mux {
		groups = "eth_tx_clk_50m", "eth_tx_en",
		"eth_txd3", "eth_txd2",
		"eth_txd1", "eth_txd0",
		"eth_rx_clk_in", "eth_rx_dv",
		"eth_rxd3", "eth_rxd2",
		"eth_rxd1", "eth_rxd0",
		"eth_mdio", "eth_mdc";
		function = "ethernet";
		};
		};
		};

		&wdt {
		compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
		};