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Commit e56b04ef authored by Lilach Edelstein's avatar Lilach Edelstein Committed by Johannes Berg
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iwlwifi: move register access lock into transport



Move the reg_lock that protects HW register access
into the transport implementation. Locking is no
longer exposed, but handled internally in grab and
release NIC access. This simplifies the users.

Signed-off-by: default avatarLilach Edelstein <lilach.edelstein@intel.com>
Signed-off-by: default avatarEmmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: default avatarJohannes Berg <johannes.berg@intel.com>
parent e139dc4a
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+2 −4
Original line number Diff line number Diff line
@@ -459,14 +459,12 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)

	base = priv->device_pointers.error_event_table;
	if (iwlagn_hw_valid_rtc_data_addr(base)) {
		spin_lock_irqsave(&priv->trans->reg_lock, flags);
		if (iwl_trans_grab_nic_access(priv->trans, true)) {
		if (iwl_trans_grab_nic_access(priv->trans, true, &flags)) {
			iwl_write32(priv->trans, HBUS_TARG_MEM_RADDR, base);
			status = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT);
			iwl_trans_release_nic_access(priv->trans);
			iwl_trans_release_nic_access(priv->trans, &flags);
			ret = 0;
		}
		spin_unlock_irqrestore(&priv->trans->reg_lock, flags);

#ifdef CONFIG_IWLWIFI_DEBUGFS
		if (ret == 0) {
+5 −12
Original line number Diff line number Diff line
@@ -353,11 +353,8 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
		ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));

	/* Make sure device is powered up for SRAM reads */
	spin_lock_irqsave(&priv->trans->reg_lock, reg_flags);
	if (!iwl_trans_grab_nic_access(priv->trans, false)) {
		spin_unlock_irqrestore(&priv->trans->reg_lock, reg_flags);
	if (!iwl_trans_grab_nic_access(priv->trans, false, &reg_flags))
		return;
	}

	/* Set starting address; reads will auto-increment */
	iwl_write32(priv->trans, HBUS_TARG_MEM_RADDR, ptr);
@@ -388,8 +385,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
		}
	}
	/* Allow device to power down */
	iwl_trans_release_nic_access(priv->trans);
	spin_unlock_irqrestore(&priv->trans->reg_lock, reg_flags);
	iwl_trans_release_nic_access(priv->trans, &reg_flags);
}

static void iwl_continuous_event_trace(struct iwl_priv *priv)
@@ -1717,9 +1713,8 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
	ptr = base + EVENT_START_OFFSET + (start_idx * event_size);

	/* Make sure device is powered up for SRAM reads */
	spin_lock_irqsave(&trans->reg_lock, reg_flags);
	if (!iwl_trans_grab_nic_access(trans, false))
		goto out_unlock;
	if (!iwl_trans_grab_nic_access(trans, false, &reg_flags))
		return pos;

	/* Set starting address; reads will auto-increment */
	iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
@@ -1757,9 +1752,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
	}

	/* Allow device to power down */
	iwl_trans_release_nic_access(trans);
out_unlock:
	spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
	iwl_trans_release_nic_access(trans, &reg_flags);
	return pos;
}

+2 −4
Original line number Diff line number Diff line
@@ -185,10 +185,8 @@ static void iwl_tt_check_exit_ct_kill(unsigned long data)
			priv->thermal_throttle.ct_kill_toggle = true;
		}
		iwl_read32(priv->trans, CSR_UCODE_DRV_GP1);
		spin_lock_irqsave(&priv->trans->reg_lock, flags);
		if (iwl_trans_grab_nic_access(priv->trans, false))
			iwl_trans_release_nic_access(priv->trans);
		spin_unlock_irqrestore(&priv->trans->reg_lock, flags);
		if (iwl_trans_grab_nic_access(priv->trans, false, &flags))
			iwl_trans_release_nic_access(priv->trans, &flags);

		/* Reschedule the ct_kill timer to occur in
		 * CT_KILL_EXIT_DURATION seconds to ensure we get a
+14 −29
Original line number Diff line number Diff line
@@ -55,13 +55,10 @@ u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
{
	u32 value = 0x5a5a5a5a;
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (iwl_trans_grab_nic_access(trans, false)) {
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
		value = iwl_read32(trans, reg);
		iwl_trans_release_nic_access(trans);
		iwl_trans_release_nic_access(trans, &flags);
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);

	return value;
}
@@ -71,12 +68,10 @@ void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (iwl_trans_grab_nic_access(trans, false)) {
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
		iwl_write32(trans, reg, value);
		iwl_trans_release_nic_access(trans);
		iwl_trans_release_nic_access(trans, &flags);
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(iwl_write_direct32);

@@ -114,12 +109,10 @@ u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
	unsigned long flags;
	u32 val = 0x5a5a5a5a;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (iwl_trans_grab_nic_access(trans, false)) {
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
		val = __iwl_read_prph(trans, ofs);
		iwl_trans_release_nic_access(trans);
		iwl_trans_release_nic_access(trans, &flags);
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
	return val;
}
EXPORT_SYMBOL_GPL(iwl_read_prph);
@@ -128,12 +121,10 @@ void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (iwl_trans_grab_nic_access(trans, false)) {
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
		__iwl_write_prph(trans, ofs, val);
		iwl_trans_release_nic_access(trans);
		iwl_trans_release_nic_access(trans, &flags);
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(iwl_write_prph);

@@ -141,13 +132,11 @@ void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (iwl_trans_grab_nic_access(trans, false)) {
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
		__iwl_write_prph(trans, ofs,
				 __iwl_read_prph(trans, ofs) | mask);
		iwl_trans_release_nic_access(trans);
		iwl_trans_release_nic_access(trans, &flags);
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(iwl_set_bits_prph);

@@ -156,13 +145,11 @@ void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (iwl_trans_grab_nic_access(trans, false)) {
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
		__iwl_write_prph(trans, ofs,
				 (__iwl_read_prph(trans, ofs) & mask) | bits);
		iwl_trans_release_nic_access(trans);
		iwl_trans_release_nic_access(trans, &flags);
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(iwl_set_bits_mask_prph);

@@ -171,12 +158,10 @@ void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (iwl_trans_grab_nic_access(trans, false)) {
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
		val = __iwl_read_prph(trans, ofs);
		__iwl_write_prph(trans, ofs, (val & ~mask));
		iwl_trans_release_nic_access(trans);
		iwl_trans_release_nic_access(trans, &flags);
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(iwl_clear_bits_prph);
+4 −13
Original line number Diff line number Diff line
@@ -466,9 +466,7 @@ static int iwl_test_indirect_read(struct iwl_test *tst, u32 addr, u32 size)
	/* Hard-coded periphery absolute address */
	if (IWL_ABS_PRPH_START <= addr &&
	    addr < IWL_ABS_PRPH_START + PRPH_END) {
			spin_lock_irqsave(&trans->reg_lock, flags);
			if (!iwl_trans_grab_nic_access(trans, false)) {
				spin_unlock_irqrestore(&trans->reg_lock, flags);
			if (!iwl_trans_grab_nic_access(trans, false, &flags)) {
				return -EIO;
			}
			iwl_write32(trans, HBUS_TARG_PRPH_RADDR,
@@ -476,8 +474,7 @@ static int iwl_test_indirect_read(struct iwl_test *tst, u32 addr, u32 size)
			for (i = 0; i < size; i += 4)
				*(u32 *)(tst->mem.addr + i) =
					iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
			iwl_trans_release_nic_access(trans);
			spin_unlock_irqrestore(&trans->reg_lock, flags);
			iwl_trans_release_nic_access(trans, &flags);
	} else { /* target memory (SRAM) */
		iwl_trans_read_mem(trans, addr, tst->mem.addr,
				   tst->mem.size / 4);
@@ -506,19 +503,13 @@ static int iwl_test_indirect_write(struct iwl_test *tst, u32 addr,
		/* Periphery writes can be 1-3 bytes long, or DWORDs */
		if (size < 4) {
			memcpy(&val, buf, size);
			spin_lock_irqsave(&trans->reg_lock, flags);
			if (!iwl_trans_grab_nic_access(trans, false)) {
				spin_unlock_irqrestore(&trans->reg_lock, flags);
			if (!iwl_trans_grab_nic_access(trans, false, &flags))
					return -EIO;
			}
			iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
				    (addr & 0x0000FFFF) |
				    ((size - 1) << 24));
			iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
			iwl_trans_release_nic_access(trans);
			/* needed after consecutive writes w/o read */
			mmiowb();
			spin_unlock_irqrestore(&trans->reg_lock, flags);
			iwl_trans_release_nic_access(trans, &flags);
		} else {
			if (size % 4)
				return -EINVAL;
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