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Commit e5566891 authored by Boris Brezillon's avatar Boris Brezillon Committed by Nicolas Ferre
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ARM: at91/dt: define the HLCDC node available on sama5d3 SoCs 



Define the HLCDC (HLCD Controller) IP available on some sama5d3 SoCs
(i.e. sama5d31, sama5d33, sama5d34 and sama5d36) in sama5d3 dtsi file.

Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: default avatarAnthony Harivel <anthony.harivel@emtrion.de>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent ee839fdd

arch/arm/boot/dts/sama5d3_lcd.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -13,6 +13,34 @@ 
/ {

	ahb {

		apb {

			hlcdc: hlcdc@f0030000 {

				compatible = "atmel,sama5d3-hlcdc";

				reg = <0xf0030000 0x2000>;

				interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;

				clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;

				clock-names = "periph_clk","sys_clk", "slow_clk";

				status = "disabled";



				hlcdc-display-controller {

					compatible = "atmel,hlcdc-display-controller";

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						#address-cells = <1>;

						#size-cells = <0>;

						reg = <0>;

					};

				};



				hlcdc_pwm: hlcdc-pwm {

					compatible = "atmel,hlcdc-pwm";

					pinctrl-names = "default";

					pinctrl-0 = <&pinctrl_lcd_pwm>;

					#pwm-cells = <3>;

				};

			};



			pinctrl@fffff200 {

				lcd {

					pinctrl_lcd_base: lcd-base-0 {