Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e52d38f4 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'lorenzo/pci/rockchip' 

  - update arm64 defconfig for Rockchip (Shawn Lin)

  - refactor Rockchip code to facilitate both root port and endpoint mode
    (Shawn Lin)

  - add Rockchip endpoint mode driver (Shawn Lin)

* lorenzo/pci/rockchip:
  arm64: defconfig: update config for Rockchip PCIe
  dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe EP driver
  PCI: rockchip: Add EP driver for Rockchip PCIe controller
  dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt
  PCI: rockchip: Split out common function to init controller
  PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT
  PCI: rockchip: Separate common code from RC driver

# Conflicts:
#	drivers/pci/host/pcie-rockchip.c
parents 1c2bef0a 7304a9a9

Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt

0 → 100644
+62 −0
Original line number Diff line number Diff line 
* Rockchip AXI PCIe Endpoint Controller DT description



Required properties:

- compatible: Should contain "rockchip,rk3399-pcie-ep"

- reg: Two register ranges as listed in the reg-names property

- reg-names: Must include the following names

	- "apb-base"

	- "mem-base"

- clocks: Must contain an entry for each entry in clock-names.

		See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

	- "aclk"

	- "aclk-perf"

	- "hclk"

	- "pm"

- resets: Must contain seven entries for each entry in reset-names.

	   See ../reset/reset.txt for details.

- reset-names: Must include the following names

	- "core"

	- "mgmt"

	- "mgmt-sticky"

	- "pipe"

	- "pm"

	- "aclk"

	- "pclk"

- pinctrl-names : The pin control state names

- pinctrl-0: The "default" pinctrl state

- phys: Must contain an phandle to a PHY for each entry in phy-names.

- phy-names: Must include 4 entries for all 4 lanes even if some of

  them won't be used for your cases. Entries are of the form "pcie-phy-N":

  where N ranges from 0 to 3.

  (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt

  for changing the #phy-cells of phy node to support it)

- rockchip,max-outbound-regions: Maximum number of outbound regions



Optional Property:

- num-lanes: number of lanes to use

- max-functions: Maximum number of functions that can be configured (default 1).



pcie0-ep: pcie@f8000000 {

	compatible = "rockchip,rk3399-pcie-ep";

	#address-cells = <3>;

	#size-cells = <2>;

	rockchip,max-outbound-regions = <16>;

	clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,

		 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;

	clock-names = "aclk", "aclk-perf",

		      "hclk", "pm";

	max-functions = /bits/ 8 <8>;

	num-lanes = <4>;

	reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;

	reg-names = "apb-base", "mem-base";

	resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,

		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,

		 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;

	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",

		      "pm", "pclk", "aclk";

	phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;

	phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";

	pinctrl-names = "default";

	pinctrl-0 = <&pcie_clkreq>;

};

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -10947,8 +10947,8 @@ M: Shawn Lin <shawn.lin@rock-chips.com> 
L:	linux-pci@vger.kernel.org

L:	linux-rockchip@lists.infradead.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/rockchip-pcie.txt

F:	drivers/pci/host/pcie-rockchip.c

F:	Documentation/devicetree/bindings/pci/rockchip-pcie*

F:	drivers/pci/host/pcie-rockchip*



PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC

M:	Linus Walleij <linus.walleij@linaro.org>

arch/arm64/configs/defconfig

+2 −1
Original line number Diff line number Diff line
@@ -78,7 +78,8 @@ CONFIG_PCIE_ARMADA_8K=y 
CONFIG_PCI_AARDVARK=y

CONFIG_PCI_TEGRA=y

CONFIG_PCIE_RCAR=y

CONFIG_PCIE_ROCKCHIP=m

CONFIG_PCIE_ROCKCHIP=y

CONFIG_PCIE_ROCKCHIP_HOST=m

CONFIG_PCI_HOST_GENERIC=y

CONFIG_PCI_XGENE=y

CONFIG_PCI_HOST_THUNDER_PEM=y

drivers/pci/host/Kconfig

+18 −1
Original line number Diff line number Diff line
@@ -179,16 +179,33 @@ config PCI_HOST_THUNDER_ECAM 
	  Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.



config PCIE_ROCKCHIP

	tristate "Rockchip PCIe controller"

	bool

	depends on PCI



config PCIE_ROCKCHIP_HOST

	tristate "Rockchip PCIe host controller"

	depends on ARCH_ROCKCHIP || COMPILE_TEST

	depends on OF

	depends on PCI_MSI_IRQ_DOMAIN

	select MFD_SYSCON

	select PCIE_ROCKCHIP

	help

	  Say Y here if you want internal PCI support on Rockchip SoC.

	  There is 1 internal PCIe port available to support GEN2 with

	  4 slots.



config PCIE_ROCKCHIP_EP

	bool "Rockchip PCIe endpoint controller"

	depends on ARCH_ROCKCHIP || COMPILE_TEST

	depends on OF

	depends on PCI_ENDPOINT

	select MFD_SYSCON

	select PCIE_ROCKCHIP

	help

	  Say Y here if you want to support Rockchip PCIe controller in

	  endpoint mode on Rockchip SoC. There is 1 internal PCIe port

	  available to support GEN2 with 4 slots.



config PCIE_MEDIATEK

	bool "MediaTek PCIe controller"

	depends on ARCH_MEDIATEK || COMPILE_TEST