Merge branch 'prcm-fixes-3.1' of git://git.pwsan.com/linux-2.6 into fixes-part-2 (e4609747) · Commits · e / devices / android_kernel_teracube_emerald

arch/arm/mach-omap2/clock44xx_data.c

+5 −4

Original line number	Diff line number	Diff line
		@@ -1605,6 +1605,7 @@ static struct clk gpmc_ick = {
		.ops = &clkops_omap2_dflt,
		.enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
		.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
		.flags = ENABLE_ON_INIT,
		.clkdm_name = "l3_2_clkdm",
		.parent = &l3_div_ck,
		.recalc = &followparent_recalc,
		@@ -3032,10 +3033,10 @@ static struct omap_clk omap44xx_clks[] = {
		CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
		CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
		CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
		CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),
		CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),
		CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),
		CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X),
		CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
		CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
		CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
		CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
		CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
		CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
		CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),

arch/arm/mach-omap2/i2c.c

+68 −0

Original line number	Diff line number	Diff line
		@@ -21,9 +21,19 @@

		#include <plat/cpu.h>
		#include <plat/i2c.h>
		#include <plat/common.h>
		#include <plat/omap_hwmod.h>

		#include "mux.h"

		/* In register I2C_CON, Bit 15 is the I2C enable bit */
		#define I2C_EN BIT(15)
		#define OMAP2_I2C_CON_OFFSET 0x24
		#define OMAP4_I2C_CON_OFFSET 0xA4

		/* Maximum microseconds to wait for OMAP module to softreset */
		#define MAX_MODULE_SOFTRESET_WAIT 10000

		void __init omap2_i2c_mux_pins(int bus_id)
		{
		char mux_name[sizeof("i2c2_scl.i2c2_scl")];
		@@ -37,3 +47,61 @@ void __init omap2_i2c_mux_pins(int bus_id)
		sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
		omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
		}

		/**
		* omap_i2c_reset - reset the omap i2c module.
		* @oh: struct omap_hwmod *
		*
		* The i2c moudle in omap2, omap3 had a special sequence to reset. The
		* sequence is:
		* - Disable the I2C.
		* - Write to SOFTRESET bit.
		* - Enable the I2C.
		* - Poll on the RESETDONE bit.
		* The sequence is implemented in below function. This is called for 2420,
		* 2430 and omap3.
		*/
		int omap_i2c_reset(struct omap_hwmod *oh)
		{
		u32 v;
		u16 i2c_con;
		int c = 0;

		if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
		i2c_con = OMAP4_I2C_CON_OFFSET;
		} else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
		i2c_con = OMAP2_I2C_CON_OFFSET;
		} else {
		WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
		oh->name);
		return -EINVAL;
		}

		/* Disable I2C */
		v = omap_hwmod_read(oh, i2c_con);
		v &= ~I2C_EN;
		omap_hwmod_write(v, oh, i2c_con);

		/* Write to the SOFTRESET bit */
		omap_hwmod_softreset(oh);

		/* Enable I2C */
		v = omap_hwmod_read(oh, i2c_con);
		v \|= I2C_EN;
		omap_hwmod_write(v, oh, i2c_con);

		/* Poll on RESETDONE bit */
		omap_test_timeout((omap_hwmod_read(oh,
		oh->class->sysc->syss_offs)
		& SYSS_RESETDONE_MASK),
		MAX_MODULE_SOFTRESET_WAIT, c);

		if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("%s: %s: softreset failed (waited %d usec)\n",
		__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
		else
		pr_debug("%s: %s: softreset in %d usec\n", __func__,
		oh->name, c);

		return 0;
		}

arch/arm/mach-omap2/omap_hwmod.c

+27 −0

Original line number	Diff line number	Diff line
		@@ -1655,6 +1655,33 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
		__raw_writel(v, oh->_mpu_rt_va + reg_offs);
		}

		/**
		* omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
		* @oh: struct omap_hwmod *
		*
		* This is a public function exposed to drivers. Some drivers may need to do
		* some settings before and after resetting the device. Those drivers after
		* doing the necessary settings could use this function to start a reset by
		* setting the SYSCONFIG.SOFTRESET bit.
		*/
		int omap_hwmod_softreset(struct omap_hwmod *oh)
		{
		u32 v;
		int ret;

		if (!oh \|\| !(oh->_sysc_cache))
		return -EINVAL;

		v = oh->_sysc_cache;
		ret = _set_softreset(oh, &v);
		if (ret)
		goto error;
		_write_sysconfig(v, oh);

		error:
		return ret;
		}

		/**
		* omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
		* @oh: struct omap_hwmod *

arch/arm/mach-omap2/omap_hwmod_2420_data.c

+8 −1

Original line number	Diff line number	Diff line
		@@ -1029,9 +1029,16 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
		static struct omap_hwmod_class i2c_class = {
		.name = "i2c",
		.sysc = &i2c_sysc,
		.rev = OMAP_I2C_IP_VERSION_1,
		.reset = &omap_i2c_reset,
		};

		static struct omap_i2c_dev_attr i2c_dev_attr;
		static struct omap_i2c_dev_attr i2c_dev_attr = {
		.flags = OMAP_I2C_FLAG_NO_FIFO \|
		OMAP_I2C_FLAG_SIMPLE_CLOCK \|
		OMAP_I2C_FLAG_16BIT_DATA_REG \|
		OMAP_I2C_FLAG_BUS_SHIFT_2,
		};

		/* I2C1 */

arch/arm/mach-omap2/omap_hwmod_2430_data.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -1078,10 +1078,15 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
		static struct omap_hwmod_class i2c_class = {
		.name = "i2c",
		.sysc = &i2c_sysc,
		.rev = OMAP_I2C_IP_VERSION_1,
		.reset = &omap_i2c_reset,
		};

		static struct omap_i2c_dev_attr i2c_dev_attr = {
		.fifo_depth = 8, /* bytes */
		.flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 \|
		OMAP_I2C_FLAG_BUS_SHIFT_2 \|
		OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
		};

		/* I2C1 */
		@@ -1092,6 +1097,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {

		static struct omap_hwmod omap2430_i2c1_hwmod = {
		.name = "i2c1",
		.flags = HWMOD_16BIT_REG,
		.mpu_irqs = omap2_i2c1_mpu_irqs,
		.sdma_reqs = omap2_i2c1_sdma_reqs,
		.main_clk = "i2chs1_fck",
		@@ -1127,6 +1133,7 @@ static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {

		static struct omap_hwmod omap2430_i2c2_hwmod = {
		.name = "i2c2",
		.flags = HWMOD_16BIT_REG,
		.mpu_irqs = omap2_i2c2_mpu_irqs,
		.sdma_reqs = omap2_i2c2_sdma_reqs,
		.main_clk = "i2chs2_fck",