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Commit e3d99845 authored by Sonika Jindal's avatar Sonika Jindal Committed by Daniel Vetter
Browse files

drm/i915/skl: Enabling PSR on Skylake 



Mainly taking care of some register offsets, otherwise things are similar to
hsw. Also, programming ddi aux to use hardcoded values for psr data select.

v2: introduce  EDP_PSR_AUX_BASE macro (Chris)
v3: Moving to HW tracking for SKL+ platforms, so activating source psr during
psr_enabling and then avoiding psr entries and exits for each frontbuffer
updates.
v4: Using SKL DDI AUX regs instead of changing PSR_AUX regs definition (Rodrigo)

Signed-off-by: default avatarSonika Jindal <sonika.jindal@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
[danvet: Drop the hunks to short-circuit sw tracking: We'd need to
push this down one level, and I don't fully trust the test coverage
yet to do so. So much prefer we pick a whitelist approach for the
cases we know work correctly.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a5094051

drivers/gpu/drm/i915/i915_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -2457,7 +2457,8 @@ struct drm_i915_cmd_table { 
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)

#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)

#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \

				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \

				 IS_SKYLAKE(dev))

#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \

				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))

#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)

drivers/gpu/drm/i915/i915_reg.h

+5 −0
Original line number Diff line number Diff line
@@ -3768,6 +3768,11 @@ enum punit_power_well { 
#define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)

#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)

#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0

#define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)

#define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)

#define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)

#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)

#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)

#define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)



/*

drivers/gpu/drm/i915/intel_psr.c

+24 −2
Original line number Diff line number Diff line
@@ -142,6 +142,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 
	struct drm_device *dev = dig_port->base.base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t aux_clock_divider;

	uint32_t aux_data_reg, aux_ctl_reg;

	int precharge = 0x3;

	static const uint8_t aux_msg[] = {

		[0] = DP_AUX_NATIVE_WRITE << 4,
@@ -164,17 +165,35 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,

				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);



	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?

				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);

	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?

				DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);



	/* Setup AUX registers */

	for (i = 0; i < sizeof(aux_msg); i += 4)

		I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,

		I915_WRITE(aux_data_reg + i,

			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));



	I915_WRITE(EDP_PSR_AUX_CTL(dev),

	if (INTEL_INFO(dev)->gen >= 9) {

		uint32_t val;



		val = I915_READ(aux_ctl_reg);

		val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;

		val |= DP_AUX_CH_CTL_TIME_OUT_1600us;

		val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;

		val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);

		/* Use hardcoded data values for PSR */

		val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;

		I915_WRITE(aux_ctl_reg, val);

	} else {

		I915_WRITE(aux_ctl_reg,

		   DP_AUX_CH_CTL_TIME_OUT_400us |

		   (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |

		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |

		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));

	}

}



static void vlv_psr_enable_source(struct intel_dp *intel_dp)

{
@@ -351,6 +370,9 @@ void intel_psr_enable(struct intel_dp *intel_dp) 


		/* Enable PSR on the panel */

		hsw_psr_enable_sink(intel_dp);



		if (INTEL_INFO(dev)->gen >= 9)

			intel_psr_activate(intel_dp);

	} else {

		vlv_psr_setup_vsc(intel_dp);