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Commit e3d0ead5 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX 



Make messages refer to all CN6XXX.

Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Signed-off-by: default avatarAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8941/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 664f1ae5

arch/mips/cavium-octeon/setup.c

+4 −3
Original line number Diff line number Diff line
@@ -1041,7 +1041,7 @@ EXPORT_SYMBOL(prom_putchar); 


void prom_free_prom_memory(void)

{

	if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {

	if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {

		/* Check for presence of Core-14449 fix.  */

		u32 insn;

		u32 *foo;
@@ -1063,8 +1063,9 @@ void prom_free_prom_memory(void) 
			panic("No PREF instruction at Core-14449 probe point.");



		if (((insn >> 16) & 0x1f) != 28)

			panic("Core-14449 WAR not in place (%04x).\n"

			      "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);

			panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"

			      "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",

			      insn);

	}

}

arch/mips/include/asm/mach-cavium-octeon/war.h

+3 −0
Original line number Diff line number Diff line
@@ -22,4 +22,7 @@ 
#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR	\

	OCTEON_IS_MODEL(OCTEON_CN6XXX)



#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */

arch/mips/mm/uasm.c

+1 −1
Original line number Diff line number Diff line
@@ -341,7 +341,7 @@ I_u3u1u2(_ldx) 
void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,

			    unsigned int c)

{

	if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)

	if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)

		/*

		 * As per erratum Core-14449, replace prefetches 0-4,

		 * 6-24 with 'pref 28'.