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Commit e3a29055 authored by Robert Beckett's avatar Robert Beckett Committed by Daniel Vetter
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drm/i915/bxt: add workaround to avoid PTE corruption 



Set TLBPF in TILECTL. This fixes an issue with BXT HW seeing
corrupted pte entries.

v2:
- move the workaround to bxt_init_clock_gating (imre)

Signed-off-by: Robert Beckett <robert.beckett@intel.com> (v1)
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8d09c812

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -1150,6 +1150,7 @@ enum skl_disp_power_wells { 
/* control register for cpu gtt access */

#define TILECTL				0x101000

#define   TILECTL_SWZCTL			(1 << 0)

#define   TILECTL_TLBPF			(1 << 1)

#define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)

#define   TILECTL_BACKSNOOP_DIS		(1 << 3)

drivers/gpu/drm/i915/intel_pm.c

+2 −0
Original line number Diff line number Diff line
@@ -110,6 +110,8 @@ static void bxt_init_clock_gating(struct drm_device *dev) 
		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |

		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);



	/* FIXME: apply on A0 only */

	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);

}



static void i915_pineview_get_mem_freq(struct drm_device *dev)