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Commit e36ea7ff authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Don't apply WaVSThreadDispatchOverride on HSW 



BSpec states that the thread override values set by
gen7_setup_fixed_func_scheduler() are invalid for HSW. So let's not
muck around with them.

Since gen7_setup_fixed_func_scheduler() now has two totally independent
parts, one for IVB and one for HSW, move the HSW part directly into
haswell_init_clock_gating().

Note tht there's another workaround by the name of
WaHSWVSRefCountFullforceMissDisable which basically claims that later
steppings don't need the fix, but since WaVSRefCountFullforceMissDisable
is listed to be needed for all steppings play it safe and keep applying
the workaround.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3aad9059

drivers/gpu/drm/i915/intel_pm.c

+4 −6
Original line number Diff line number Diff line
@@ -4658,7 +4658,7 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 
	uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);



	/*

	 * WaVSThreadDispatchOverride:ivb,hsw

	 * WaVSThreadDispatchOverride:ivb

	 *

	 * This actually overrides the dispatch

	 * mode for all thread types.
@@ -4668,10 +4668,6 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 
	reg |= GEN7_FF_VS_SCHED_HW;

	reg |= GEN7_FF_DS_SCHED_HW;



	/* WaVSRefCountFullforceMissDisable:hsw */

	if (IS_HASWELL(dev_priv->dev))

		reg &= ~GEN7_FF_VS_REF_CNT_FFME;



	I915_WRITE(GEN7_FF_THREAD_MODE, reg);

}
@@ -4782,7 +4778,9 @@ static void haswell_init_clock_gating(struct drm_device *dev) 
			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);



	gen7_setup_fixed_func_scheduler(dev_priv);

	/* WaVSRefCountFullforceMissDisable:hsw */

	I915_WRITE(GEN7_FF_THREAD_MODE,

		   I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);



	/* WaDisable4x2SubspanOptimization:hsw */

	I915_WRITE(CACHE_MODE_1,