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Commit e2d54fe7 authored by Roger Quadros's avatar Roger Quadros Committed by Tony Lindgren
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ARM: DRA7: hwmod_data: Prevent wait_target_disable error for usb_otg_ss 



It seems that if L3_INIT clkdomain is kept in HW_AUTO while usb_otg_ss
is in use then there are random chances that the usb_otg_ss module
will fail to completely idle. i.e. IDLEST = 0x2 instead of 0x3.

Preventing L3_INIT from HW_AUTO while usb_otg_ss module is in use
fixes this issue.

We don't know yet if usb_otg_ss instances 3 and 4 are affected by this
issue or not so don't add this flag for those instances.

Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent a2416238

arch/arm/mach-omap2/omap_hwmod_7xx_data.c

+2 −0
Original line number Diff line number Diff line
@@ -2701,6 +2701,7 @@ static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = { 
	.class		= &dra7xx_usb_otg_ss_hwmod_class,

	.clkdm_name	= "l3init_clkdm",

	.main_clk	= "dpll_core_h13x2_ck",

	.flags		= HWMOD_CLKDM_NOAUTO,

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
@@ -2722,6 +2723,7 @@ static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = { 
	.class		= &dra7xx_usb_otg_ss_hwmod_class,

	.clkdm_name	= "l3init_clkdm",

	.main_clk	= "dpll_core_h13x2_ck",

	.flags		= HWMOD_CLKDM_NOAUTO,

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,