Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e2d214ae authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Make IS_BROXTON only take dev_priv 



Saves 1392 bytes of .rodata strings.

Also change a few function/macro prototypes in i915_gem_gtt.c
from dev to dev_priv where it made more sense to do so.

v2: Add parantheses around dev_priv. (Ville Syrjala)
v3: Mention function prototype changes. (David Weinehall)

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: default avatarJani Nikula <jani.nikula@linux.intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
parent d9486e65

drivers/gpu/drm/i915/i915_drv.c

+1 −1
Original line number Diff line number Diff line
@@ -2414,7 +2414,7 @@ static int intel_runtime_resume(struct device *kdev) 
	if (IS_GEN6(dev_priv))

		intel_init_pch_refclk(dev);



	if (IS_BROXTON(dev)) {

	if (IS_BROXTON(dev_priv)) {

		bxt_disable_dc9(dev_priv);

		bxt_display_core_init(dev_priv, true);

		if (dev_priv->csr.dmc_payload &&

drivers/gpu/drm/i915/i915_drv.h

+3 −2
Original line number Diff line number Diff line
@@ -2660,7 +2660,7 @@ struct drm_i915_cmd_table { 
#define IS_HASWELL(dev_priv)	((dev_priv)->info.is_haswell)

#define IS_BROADWELL(dev_priv)	((dev_priv)->info.is_broadwell)

#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.is_skylake)

#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)

#define IS_BROXTON(dev_priv)	((dev_priv)->info.is_broxton)

#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.is_kabylake)

#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)

#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
@@ -2720,7 +2720,8 @@ struct drm_i915_cmd_table { 
#define BXT_REVID_B0		0x3

#define BXT_REVID_C0		0x9



#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))

#define IS_BXT_REVID(dev_priv, since, until) \

	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))



#define KBL_REVID_A0		0x0

#define KBL_REVID_B0		0x1

drivers/gpu/drm/i915/i915_gem_gtt.c

+21 −19
Original line number Diff line number Diff line
@@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p) 
/* We use the flushing unmap only with ppgtt structures:

 * page directories, page tables and scratch pages.

 */

static void kunmap_page_dma(struct drm_device *dev, void *vaddr)

static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)

{

	/* There are only few exceptions for gen >=6. chv and bxt.

	 * And we are not sure about the latter so play safe for now.

	 */

	if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))

	if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))

		drm_clflush_virt_range(vaddr, PAGE_SIZE);



	kunmap_atomic(vaddr);

}



#define kmap_px(px) kmap_page_dma(px_base(px))

#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))

#define kunmap_px(ppgtt, vaddr) \

		kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))



#define setup_px(dev, px) setup_page_dma((dev), px_base(px))

#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))

#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))

#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))

#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))

#define fill32_px(dev_priv, px, v) \

		fill_page_dma_32((dev_priv), px_base(px), (v))



static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,

			  const uint64_t val)

static void fill_page_dma(struct drm_i915_private *dev_priv,

			  struct i915_page_dma *p, const uint64_t val)

{

	int i;

	uint64_t * const vaddr = kmap_page_dma(p);
@@ -401,17 +403,17 @@ static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p, 
	for (i = 0; i < 512; i++)

		vaddr[i] = val;



	kunmap_page_dma(dev, vaddr);

	kunmap_page_dma(dev_priv, vaddr);

}



static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,

			     const uint32_t val32)

static void fill_page_dma_32(struct drm_i915_private *dev_priv,

			     struct i915_page_dma *p, const uint32_t val32)

{

	uint64_t v = val32;



	v = v << 32 | val32;



	fill_page_dma(dev, p, v);

	fill_page_dma(dev_priv, p, v);

}



static int
@@ -474,7 +476,7 @@ static void gen8_initialize_pt(struct i915_address_space *vm, 
	scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,

				      I915_CACHE_LLC, true);



	fill_px(vm->dev, pt, scratch_pte);

	fill_px(to_i915(vm->dev), pt, scratch_pte);

}



static void gen6_initialize_pt(struct i915_address_space *vm,
@@ -487,7 +489,7 @@ static void gen6_initialize_pt(struct i915_address_space *vm, 
	scratch_pte = vm->pte_encode(vm->scratch_page.daddr,

				     I915_CACHE_LLC, true, 0);



	fill32_px(vm->dev, pt, scratch_pte);

	fill32_px(to_i915(vm->dev), pt, scratch_pte);

}



static struct i915_page_directory *alloc_pd(struct drm_device *dev)
@@ -534,7 +536,7 @@ static void gen8_initialize_pd(struct i915_address_space *vm, 


	scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);



	fill_px(vm->dev, pd, scratch_pde);

	fill_px(to_i915(vm->dev), pd, scratch_pde);

}



static int __pdp_init(struct drm_device *dev,
@@ -615,7 +617,7 @@ static void gen8_initialize_pdp(struct i915_address_space *vm, 


	scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);



	fill_px(vm->dev, pdp, scratch_pdpe);

	fill_px(to_i915(vm->dev), pdp, scratch_pdpe);

}



static void gen8_initialize_pml4(struct i915_address_space *vm,
@@ -626,7 +628,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm, 
	scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),

					  I915_CACHE_LLC);



	fill_px(vm->dev, pml4, scratch_pml4e);

	fill_px(to_i915(vm->dev), pml4, scratch_pml4e);

}



static void
@@ -2137,7 +2139,7 @@ static void gtt_write_workarounds(struct drm_device *dev) 
		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);

	else if (IS_SKYLAKE(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);

	else if (IS_BROXTON(dev))

	else if (IS_BROXTON(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);

}
@@ -2918,7 +2920,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) 
	 * resort to an uncached mapping. The WC issue is easily caught by the

	 * readback check when writing GTT PTE entries.

	 */

	if (IS_BROXTON(ggtt->base.dev))

	if (IS_BROXTON(to_i915(ggtt->base.dev)))

		ggtt->gsm = ioremap_nocache(phys_addr, size);

	else

		ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3290,7 +3292,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) 
	ggtt->base.closed = false;



	if (INTEL_INFO(dev)->gen >= 8) {

		if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))

		if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))

			chv_setup_private_ppat(dev_priv);

		else

			bdw_setup_private_ppat(dev_priv);

drivers/gpu/drm/i915/i915_irq.c

+1 −1
Original line number Diff line number Diff line
@@ -4594,7 +4594,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) 
		dev->driver->irq_uninstall = gen8_irq_uninstall;

		dev->driver->enable_vblank = gen8_enable_vblank;

		dev->driver->disable_vblank = gen8_disable_vblank;

		if (IS_BROXTON(dev))

		if (IS_BROXTON(dev_priv))

			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;

		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))

			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;

drivers/gpu/drm/i915/intel_ddi.c

+2 −2
Original line number Diff line number Diff line
@@ -2509,7 +2509,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) 
	 * configuration so that we use the proper lane count for our

	 * calculations.

	 */

	if (IS_BROXTON(dev) && port == PORT_A) {

	if (IS_BROXTON(dev_priv) && port == PORT_A) {

		if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {

			DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");

			intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
@@ -2533,7 +2533,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) 
		 * On BXT A0/A1, sw needs to activate DDIA HPD logic and

		 * interrupts to check the external panel connection.

		 */

		if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)

		if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B)

			dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;

		else

			dev_priv->hotplug.irq_port[port] = intel_dig_port;