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Commit e288881b authored by Juha-Pekka Heikkila's avatar Juha-Pekka Heikkila Committed by Ville Syrjälä
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drm/i915: dspaddr_offset doesn't need to be more than local variable 



Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()

Signed-off-by: default avatarJuha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1508270891-22186-3-git-send-email-juhapekka.heikkila@gmail.com
parent bf0a5d4b

drivers/gpu/drm/i915/intel_display.c

+6 −9
Original line number Diff line number Diff line
@@ -3289,7 +3289,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, 
				      const struct intel_plane_state *plane_state)

{

	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_framebuffer *fb = plane_state->base.fb;

	enum plane plane = primary->plane;

	u32 linear_offset;
@@ -3298,13 +3297,14 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, 
	int x = plane_state->main.x;

	int y = plane_state->main.y;

	unsigned long irqflags;

	u32 dspaddr_offset;



	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);



	if (INTEL_GEN(dev_priv) >= 4)

		crtc->dspaddr_offset = plane_state->main.offset;

		dspaddr_offset = plane_state->main.offset;

	else

		crtc->dspaddr_offset = linear_offset;

		dspaddr_offset = linear_offset;



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
@@ -3330,18 +3330,18 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, 
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		I915_WRITE_FW(DSPSURF(plane),

			      intel_plane_ggtt_offset(plane_state) +

			      crtc->dspaddr_offset);

			      dspaddr_offset);

		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);

	} else if (INTEL_GEN(dev_priv) >= 4) {

		I915_WRITE_FW(DSPSURF(plane),

			      intel_plane_ggtt_offset(plane_state) +

			      crtc->dspaddr_offset);

			      dspaddr_offset);

		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);

		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);

	} else {

		I915_WRITE_FW(DSPADDR(plane),

			      intel_plane_ggtt_offset(plane_state) +

			      crtc->dspaddr_offset);

			      dspaddr_offset);

	}

	POSTING_READ_FW(reg);
@@ -3546,7 +3546,6 @@ static void skylake_update_primary_plane(struct intel_plane *plane, 
					 const struct intel_plane_state *plane_state)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_framebuffer *fb = plane_state->base.fb;

	enum plane_id plane_id = plane->id;

	enum pipe pipe = plane->pipe;
@@ -3572,8 +3571,6 @@ static void skylake_update_primary_plane(struct intel_plane *plane, 
	dst_w--;

	dst_h--;



	crtc->dspaddr_offset = surf_addr;



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {

drivers/gpu/drm/i915/intel_drv.h

+0 −5
Original line number Diff line number Diff line
@@ -808,11 +808,6 @@ struct intel_crtc { 
	unsigned long long enabled_power_domains;

	struct intel_overlay *overlay;



	/* Display surface base address adjustement for pageflips. Note that on

	 * gen4+ this only adjusts up to a tile, offsets within a tile are

	 * handled in the hw itself (with the TILEOFF register). */

	u32 dspaddr_offset;



	struct intel_crtc_state *config;



	/* global reset count when the last flip was submitted */