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Commit e2707285 authored by Andy Yan's avatar Andy Yan Committed by Cyrille Pitchen
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mtd: spi-nor: add a quad_enable callback in struct flash_info 



Some manufacturers may use different bit to set QE on different
memories.

The GD25Q256 from GigaDevice is an example, which uses S6(bit 6
of the Status Register-1) to set QE, which is different with
other supported memories from GigaDevice that use S9(bit 1 of
the Status Register-2). This makes it is impossible to select
the quad enable method by distinguishing the MFR. This patch
introduce a quad_enable function which can be set per memory
in the flash_info list table.

Signed-off-by: default avatarAndy Yan <andy.yan@rock-chips.com>
Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
parent 70597eec

drivers/mtd/spi-nor/spi-nor.c

+11 −0
Original line number Diff line number Diff line
@@ -89,6 +89,8 @@ struct flash_info { 
#define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */

#define SPI_NOR_SKIP_SFDP	BIT(13)	/* Skip parsing of SFDP tables */

#define USE_CLSR		BIT(14)	/* use CLSR command */



	int	(*quad_enable)(struct spi_nor *nor);

};



#define JEDEC_MFR(info)	((info)->id[0])
@@ -2426,6 +2428,15 @@ static int spi_nor_init_params(struct spi_nor *nor, 
			params->quad_enable = spansion_quad_enable;

			break;

		}



		/*

		 * Some manufacturer like GigaDevice may use different

		 * bit to set QE on different memories, so the MFR can't

		 * indicate the quad_enable method for this case, we need

		 * set it in flash info list.

		 */

		if (info->quad_enable)

			params->quad_enable = info->quad_enable;

	}



	/* Override the parameters with data read from SFDP tables. */