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Commit e1487888 authored by Chris Brandt's avatar Chris Brandt Committed by David S. Miller
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net: ethernet: renesas: sh_eth: add POST registers for rz 



Due to a mistake in the hardware manual, the FWSLC and POST1-4 registers
were not documented and left out of the driver for RZ/A making the CAM
feature non-operational.
Additionally, when the offset values for POST1-4 are left blank, the driver
attempts to set them using an offset of 0xFFFF which can cause a memory
corruption or panic.

This patch fixes the panic and properly enables CAM.

Reported-by: default avatarDaniel Palmer <daniel@0x0f.com>
Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Acked-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c2f57fb9

drivers/net/ethernet/renesas/sh_eth.c

+7 −0
Original line number Diff line number Diff line
@@ -201,9 +201,14 @@ static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 


	[ARSTR]		= 0x0000,

	[TSU_CTRST]	= 0x0004,

	[TSU_FWSLC]	= 0x0038,

	[TSU_VTAG0]	= 0x0058,

	[TSU_ADSBSY]	= 0x0060,

	[TSU_TEN]	= 0x0064,

	[TSU_POST1]	= 0x0070,

	[TSU_POST2]	= 0x0074,

	[TSU_POST3]	= 0x0078,

	[TSU_POST4]	= 0x007c,

	[TSU_ADRH0]	= 0x0100,



	[TXNLCR0]	= 0x0080,
@@ -2786,6 +2791,8 @@ static void sh_eth_tsu_init(struct sh_eth_private *mdp) 
{

	if (sh_eth_is_rz_fast_ether(mdp)) {

		sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */

		sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,

				 TSU_FWSLC);	/* Enable POST registers */

		return;

	}