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Commit e128b4f4 authored by Borislav Petkov's avatar Borislav Petkov Committed by Ingo Molnar
Browse files

x86/mce/AMD: Save an indentation level in prepare_threshold_block() 



Do the !SMCA work first and then save us an indentation level for the
SMCA code.

No functionality change.

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1462971509-3856-4-git-send-email-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 32544f06

arch/x86/kernel/cpu/mcheck/mce_amd.c

+38 −40
Original line number Diff line number Diff line
@@ -343,6 +343,7 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 
			int offset, u32 misc_high)

{

	unsigned int cpu = smp_processor_id();

	u32 smca_low, smca_high, smca_addr;

	struct threshold_block b;

	int new;
@@ -361,37 +362,36 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 


	b.interrupt_enable = 1;



	if (mce_flags.smca) {

		u32 smca_low, smca_high;

		u32 smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank);

	if (!mce_flags.smca) {

		new = (misc_high & MASK_LVTOFF_HI) >> 20;

		goto set_offset;

	}



	smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank);



	if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) {

		/*

			 * OS is required to set the MCAX bit to acknowledge

			 * that it is now using the new MSR ranges and new

			 * registers under each bank. It also means that the OS

			 * will configure deferred errors in the new MCx_CONFIG

			 * register. If the bit is not set, uncorrectable errors

			 * will cause a system panic.

		 * OS is required to set the MCAX bit to acknowledge that it is

		 * now using the new MSR ranges and new registers under each

		 * bank. It also means that the OS will configure deferred

		 * errors in the new MCx_CONFIG register. If the bit is not set,

		 * uncorrectable errors will cause a system panic.

		 *

			 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of

			 * the MSR.)

		 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)

		 */

		smca_high |= BIT(0);



		/*

			 * SMCA logs Deferred Error information in

			 * MCA_DE{STAT,ADDR} registers with the option of

			 * additionally logging to MCA_{STATUS,ADDR} if

			 * MCA_CONFIG[LogDeferredInMcaStat] is set.

		 * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR}

		 * registers with the option of additionally logging to

		 * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set.

		 *

			 * This bit is usually set by BIOS to retain the old

			 * behavior for OSes that don't use the new registers.

			 * Linux supports the new registers so let's disable

			 * that additional logging here.

		 * This bit is usually set by BIOS to retain the old behavior

		 * for OSes that don't use the new registers. Linux supports the

		 * new registers so let's disable that additional logging here.

		 *

			 * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in

			 * the high portion of the MSR).

		 * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high

		 * portion of the MSR).

		 */

		smca_high &= ~BIT(2);
@@ -403,10 +403,8 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 
		goto out;



	new = (smca_low & SMCA_THR_LVT_OFF) >> 12;

	} else {

		new = (misc_high & MASK_LVTOFF_HI) >> 20;

	}



set_offset:

	offset = setup_APIC_mce_threshold(offset, new);



	if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))