Loading drivers/gpu/drm/i915/i915_dma.c +3 −3 Original line number Diff line number Diff line Loading @@ -1602,9 +1602,9 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) } } div_u64(diff, diff1); diff = div_u64(diff, diff1); ret = ((m * diff) + c); div_u64(ret, 10); ret = div_u64(ret, 10); dev_priv->last_count1 = total_count; dev_priv->last_time1 = now; Loading Loading @@ -1673,7 +1673,7 @@ void i915_update_gfx_val(struct drm_i915_private *dev_priv) /* More magic constants... */ diff = diff * 1181; div_u64(diff, diffms * 10); diff = div_u64(diff, diffms * 10); dev_priv->gfx_power = diff; } Loading drivers/gpu/drm/i915/i915_gem.c +1 −1 Original line number Diff line number Diff line Loading @@ -2533,7 +2533,7 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj) I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); break; case 3: if (obj_priv->fence_reg > 8) if (obj_priv->fence_reg >= 8) fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; else case 2: Loading drivers/gpu/drm/i915/intel_sdvo.c +6 −9 Original line number Diff line number Diff line Loading @@ -2156,8 +2156,7 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) return true; err: intel_sdvo_destroy_enhance_property(connector); kfree(intel_sdvo_connector); intel_sdvo_destroy(connector); return false; } Loading Loading @@ -2230,8 +2229,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) return true; err: intel_sdvo_destroy_enhance_property(connector); kfree(intel_sdvo_connector); intel_sdvo_destroy(connector); return false; } Loading Loading @@ -2509,11 +2507,10 @@ static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, uint16_t response; } enhancements; if (!intel_sdvo_get_value(intel_sdvo, enhancements.response = 0; intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, &enhancements, sizeof(enhancements))) return false; &enhancements, sizeof(enhancements)); if (enhancements.response == 0) { DRM_DEBUG_KMS("No enhancement is supported\n"); return true; Loading Loading
drivers/gpu/drm/i915/i915_dma.c +3 −3 Original line number Diff line number Diff line Loading @@ -1602,9 +1602,9 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) } } div_u64(diff, diff1); diff = div_u64(diff, diff1); ret = ((m * diff) + c); div_u64(ret, 10); ret = div_u64(ret, 10); dev_priv->last_count1 = total_count; dev_priv->last_time1 = now; Loading Loading @@ -1673,7 +1673,7 @@ void i915_update_gfx_val(struct drm_i915_private *dev_priv) /* More magic constants... */ diff = diff * 1181; div_u64(diff, diffms * 10); diff = div_u64(diff, diffms * 10); dev_priv->gfx_power = diff; } Loading
drivers/gpu/drm/i915/i915_gem.c +1 −1 Original line number Diff line number Diff line Loading @@ -2533,7 +2533,7 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj) I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); break; case 3: if (obj_priv->fence_reg > 8) if (obj_priv->fence_reg >= 8) fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; else case 2: Loading
drivers/gpu/drm/i915/intel_sdvo.c +6 −9 Original line number Diff line number Diff line Loading @@ -2156,8 +2156,7 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) return true; err: intel_sdvo_destroy_enhance_property(connector); kfree(intel_sdvo_connector); intel_sdvo_destroy(connector); return false; } Loading Loading @@ -2230,8 +2229,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) return true; err: intel_sdvo_destroy_enhance_property(connector); kfree(intel_sdvo_connector); intel_sdvo_destroy(connector); return false; } Loading Loading @@ -2509,11 +2507,10 @@ static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, uint16_t response; } enhancements; if (!intel_sdvo_get_value(intel_sdvo, enhancements.response = 0; intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, &enhancements, sizeof(enhancements))) return false; &enhancements, sizeof(enhancements)); if (enhancements.response == 0) { DRM_DEBUG_KMS("No enhancement is supported\n"); return true; Loading