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Commit e095ee6b authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Greg Kroah-Hartman
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serial: sh-sci: Replace regmap array with port parameters 



Turn the regmap two-dimensional array to an array of port parameters and
store a pointer to the port parameters in the sci_port structure. This
will allow handling additional port type dependent parameters.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 40b34ddb

drivers/tty/serial/sh-sci.c

+155 −123
Original line number Diff line number Diff line
@@ -101,10 +101,19 @@ enum SCI_CLKS { 
	for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--)	\

		if ((_port)->sampling_rate_mask & SCI_SR((_sr)))



struct plat_sci_reg {

	u8 offset, size;

};



struct sci_port_params {

	const struct plat_sci_reg regs[SCIx_NR_REGS];

};



struct sci_port {

	struct uart_port	port;



	/* Platform configuration */

	const struct sci_port_params *params;

	struct plat_sci_port	*cfg;

	unsigned int		overrun_reg;

	unsigned int		overrun_mask;
@@ -156,16 +165,13 @@ to_sci_port(struct uart_port *uart) 
	return container_of(uart, struct sci_port, port);

}



struct plat_sci_reg {

	u8 offset, size;

};



static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {

static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {

	/*

	 * Common SCI definitions, dependent on the port's regshift

	 * value.

	 */

	[SCIx_SCI_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00,  8 },

			[SCBRR]		= { 0x01,  8 },

			[SCSCR]		= { 0x02,  8 },
@@ -173,11 +179,13 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCxSR]		= { 0x04,  8 },

			[SCxRDR]	= { 0x05,  8 },

		},

	},



	/*

	 * Common definitions for legacy IrDA ports.

	 */

	[SCIx_IRDA_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00,  8 },

			[SCBRR]		= { 0x02,  8 },

			[SCSCR]		= { 0x04,  8 },
@@ -187,11 +195,13 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCFCR]		= { 0x0c,  8 },

			[SCFDR]		= { 0x0e, 16 },

		},

	},



	/*

	 * Common SCIFA definitions.

	 */

	[SCIx_SCIFA_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00, 16 },

			[SCBRR]		= { 0x04,  8 },

			[SCSCR]		= { 0x08, 16 },
@@ -203,11 +213,13 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCPCR]		= { 0x30, 16 },

			[SCPDR]		= { 0x34, 16 },

		},

	},



	/*

	 * Common SCIFB definitions.

	 */

	[SCIx_SCIFB_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00, 16 },

			[SCBRR]		= { 0x04,  8 },

			[SCSCR]		= { 0x08, 16 },
@@ -220,12 +232,14 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCPCR]		= { 0x30, 16 },

			[SCPDR]		= { 0x34, 16 },

		},

	},



	/*

	 * Common SH-2(A) SCIF definitions for ports with FIFO data

	 * count registers.

	 */

	[SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00, 16 },

			[SCBRR]		= { 0x04,  8 },

			[SCSCR]		= { 0x08, 16 },
@@ -237,11 +251,13 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCSPTR]	= { 0x20, 16 },

			[SCLSR]		= { 0x24, 16 },

		},

	},



	/*

	 * Common SH-3 SCIF definitions.

	 */

	[SCIx_SH3_SCIF_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00,  8 },

			[SCBRR]		= { 0x02,  8 },

			[SCSCR]		= { 0x04,  8 },
@@ -251,11 +267,13 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCFCR]		= { 0x0c,  8 },

			[SCFDR]		= { 0x0e, 16 },

		},

	},



	/*

	 * Common SH-4(A) SCIF(B) definitions.

	 */

	[SCIx_SH4_SCIF_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00, 16 },

			[SCBRR]		= { 0x04,  8 },

			[SCSCR]		= { 0x08, 16 },
@@ -267,12 +285,14 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCSPTR]	= { 0x20, 16 },

			[SCLSR]		= { 0x24, 16 },

		},

	},



	/*

	 * Common SCIF definitions for ports with a Baud Rate Generator for

	 * External Clock (BRG).

	 */

	[SCIx_SH4_SCIF_BRG_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00, 16 },

			[SCBRR]		= { 0x04,  8 },

			[SCSCR]		= { 0x08, 16 },
@@ -286,11 +306,13 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCDL]		= { 0x30, 16 },

			[SCCKS]		= { 0x34, 16 },

		},

	},



	/*

	 * Common HSCIF definitions.

	 */

	[SCIx_HSCIF_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00, 16 },

			[SCBRR]		= { 0x04,  8 },

			[SCSCR]		= { 0x08, 16 },
@@ -305,12 +327,14 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCDL]		= { 0x30, 16 },

			[SCCKS]		= { 0x34, 16 },

		},

	},



	/*

	 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR

	 * register.

	 */

	[SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00, 16 },

			[SCBRR]		= { 0x04,  8 },

			[SCSCR]		= { 0x08, 16 },
@@ -321,12 +345,14 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCFDR]		= { 0x1c, 16 },

			[SCLSR]		= { 0x24, 16 },

		},

	},



	/*

	 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data

	 * count registers.

	 */

	[SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00, 16 },

			[SCBRR]		= { 0x04,  8 },

			[SCSCR]		= { 0x08, 16 },
@@ -340,12 +366,14 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCSPTR]	= { 0x24, 16 },

			[SCLSR]		= { 0x28, 16 },

		},

	},



	/*

	 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR

	 * registers.

	 */

	[SCIx_SH7705_SCIF_REGTYPE] = {

		.regs = {

			[SCSMR]		= { 0x00, 16 },

			[SCBRR]		= { 0x04,  8 },

			[SCSCR]		= { 0x08, 16 },
@@ -355,9 +383,10 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 
			[SCFCR]		= { 0x18, 16 },

			[SCFDR]		= { 0x1c, 16 },

		},

	},

};



#define sci_getreg(up, offset)		(sci_regmap[to_sci_port(up)->cfg->regtype] + offset)

#define sci_getreg(up, offset)		(&to_sci_port(up)->params->regs[offset])



/*

 * The "offset" here is rather misleading, in that it refers to an enum
@@ -2557,6 +2586,8 @@ static int sci_init_single(struct platform_device *dev, 
			return ret;

	}



	sci_port->params = &sci_port_params[p->regtype];



	switch (p->type) {

	case PORT_SCIFB:

		port->fifosize = 256;
@@ -3069,6 +3100,7 @@ static int __init early_console_setup(struct earlycon_device *device, 
	sci_ports[0].cfg = &port_cfg;

	sci_ports[0].cfg->type = type;

	sci_probe_regmap(sci_ports[0].cfg);

	sci_ports[0].params = &sci_port_params[sci_ports[0].cfg->regtype];

	port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);

	sci_serial_out(&sci_ports[0].port, SCSCR,

		       SCSCR_RE | SCSCR_TE | port_cfg.scscr);