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Commit df7939ae authored by Glauber de Oliveira Costa's avatar Glauber de Oliveira Costa Committed by Ingo Molnar
Browse files

x86: wrap esr setting up in i386 in lapic_setup_esr 



it is a little bit more complicated than x86_64 due to erratas and
other stuff, but its existance will ease integration

Signed-off-by: default avatarGlauber Costa <gcosta@redhat.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent ea0cadbf

arch/x86/kernel/apic_32.c

+40 −33
Original line number Original line Diff line number Diff line
@@ -897,12 +897,50 @@ void __init init_bsp_APIC(void) 
	apic_write_around(APIC_LVT1, value);

	apic_write_around(APIC_LVT1, value);

}

}





void __cpuinit lapic_setup_esr(void)

{

	unsigned long oldvalue, value, maxlvt;

	if (lapic_is_integrated() && !esr_disable) {

		/* !82489DX */

		maxlvt = lapic_get_maxlvt();

		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */

			apic_write(APIC_ESR, 0);

		oldvalue = apic_read(APIC_ESR);



		/* enables sending errors */

		value = ERROR_APIC_VECTOR;

		apic_write_around(APIC_LVTERR, value);

		/*

		 * spec says clear errors after enabling vector.

		 */

		if (maxlvt > 3)

			apic_write(APIC_ESR, 0);

		value = apic_read(APIC_ESR);

		if (value != oldvalue)

			apic_printk(APIC_VERBOSE, "ESR value before enabling "

				"vector: 0x%08lx  after: 0x%08lx\n",

				oldvalue, value);

	} else {

		if (esr_disable)

			/*

			 * Something untraceable is creating bad interrupts on

			 * secondary quads ... for the moment, just leave the

			 * ESR disabled - we can't do anything useful with the

			 * errors anyway - mbligh

			 */

			printk(KERN_INFO "Leaving ESR disabled.\n");

		else

			printk(KERN_INFO "No ESR for 82489DX.\n");

	}

}





/**

/**

 * setup_local_APIC - setup the local APIC

 * setup_local_APIC - setup the local APIC

 */

 */

void __cpuinit setup_local_APIC(void)

void __cpuinit setup_local_APIC(void)

{

{

	unsigned long oldvalue, value, maxlvt, integrated;

	unsigned long value, integrated;

	int i, j;

	int i, j;





	/* Pound the ESR really hard over the head with a big hammer - mbligh */

	/* Pound the ESR really hard over the head with a big hammer - mbligh */
@@ -1027,38 +1065,7 @@ void __cpuinit setup_local_APIC(void) 
		value |= APIC_LVT_LEVEL_TRIGGER;

		value |= APIC_LVT_LEVEL_TRIGGER;

	apic_write_around(APIC_LVT1, value);

	apic_write_around(APIC_LVT1, value);





	if (integrated && !esr_disable) {

	lapic_setup_esr();

		/* !82489DX */

		maxlvt = lapic_get_maxlvt();

		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */

			apic_write(APIC_ESR, 0);

		oldvalue = apic_read(APIC_ESR);



		/* enables sending errors */

		value = ERROR_APIC_VECTOR;

		apic_write_around(APIC_LVTERR, value);

		/*

		 * spec says clear errors after enabling vector.

		 */

		if (maxlvt > 3)

			apic_write(APIC_ESR, 0);

		value = apic_read(APIC_ESR);

		if (value != oldvalue)

			apic_printk(APIC_VERBOSE, "ESR value before enabling "

				"vector: 0x%08lx  after: 0x%08lx\n",

				oldvalue, value);

	} else {

		if (esr_disable)

			/*

			 * Something untraceable is creating bad interrupts on

			 * secondary quads ... for the moment, just leave the

			 * ESR disabled - we can't do anything useful with the

			 * errors anyway - mbligh

			 */

			printk(KERN_INFO "Leaving ESR disabled.\n");

		else

			printk(KERN_INFO "No ESR for 82489DX.\n");

	}





	/* Disable the local apic timer */

	/* Disable the local apic timer */

	value = apic_read(APIC_LVTT);

	value = apic_read(APIC_LVTT);