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Commit df05a303 authored by Andrew Victor's avatar Andrew Victor Committed by Pierre Ossman
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AT91 MMC 4 : Interrupt handler cleanup 



This patch simplifies the AT91RM9200 MMC interrupt handler code so that
it doesn't re-read the Interrupt Status and Interrupt Mask registers
multiple times.

Also defined AT91_MCI_ERRORS instead of using the hard-coded 0xffff0000.

Signed-off-by: default avatarAndrew Victor <andrew@sanpeople.com>
Signed-off-by: default avatarPierre Ossman <drzeus@drzeus.cx>
parent 3dd3b039

drivers/mmc/at91_mci.c

+43 −45
Original line number Original line Diff line number Diff line
@@ -83,7 +83,9 @@ 
#define FL_SENT_COMMAND	(1 << 0)

#define FL_SENT_COMMAND	(1 << 0)

#define FL_SENT_STOP	(1 << 1)

#define FL_SENT_STOP	(1 << 1)







#define AT91_MCI_ERRORS	(AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE	\

		| AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE		\

		| AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)			





#define at91_mci_read(host, reg)	__raw_readl((host)->baseaddr + (reg))

#define at91_mci_read(host, reg)	__raw_readl((host)->baseaddr + (reg))

#define at91_mci_write(host, reg, val)	__raw_writel((val), (host)->baseaddr + (reg))

#define at91_mci_write(host, reg, val)	__raw_writel((val), (host)->baseaddr + (reg))
@@ -507,7 +509,7 @@ static void at91mci_process_command(struct at91mci_host *host, struct mmc_comman 
	pr_debug("setting ier to %08X\n", ier);

	pr_debug("setting ier to %08X\n", ier);





	/* Stop on errors or the required value */

	/* Stop on errors or the required value */

	at91_mci_write(host, AT91_MCI_IER, 0xffff0000 | ier);

	at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);

}

}





/*

/*
@@ -652,17 +654,18 @@ static irqreturn_t at91_mci_irq(int irq, void *devid) 
{

{

	struct at91mci_host *host = devid;

	struct at91mci_host *host = devid;

	int completed = 0;

	int completed = 0;



	unsigned int int_status, int_mask;

	unsigned int int_status;





	int_status = at91_mci_read(host, AT91_MCI_SR);

	int_status = at91_mci_read(host, AT91_MCI_SR);

	pr_debug("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(host, AT91_MCI_IMR),

	int_mask = at91_mci_read(host, AT91_MCI_IMR);

		int_status & at91_mci_read(host, AT91_MCI_IMR));

	

	

	if ((int_status & at91_mci_read(host, AT91_MCI_IMR)) & 0xffff0000)

	pr_debug("MCI irq: status = %08X, %08lX, %08lX\n", int_status, int_mask,

		completed = 1;

		int_status & int_mask);

	

	int_status = int_status & int_mask;





	int_status &= at91_mci_read(host, AT91_MCI_IMR);

	if (int_status & AT91_MCI_ERRORS) {

		completed = 1;

		

		

		if (int_status & AT91_MCI_UNRE)

		if (int_status & AT91_MCI_UNRE)

			pr_debug("MMC: Underrun error\n");

			pr_debug("MMC: Underrun error\n");
@@ -682,9 +685,9 @@ static irqreturn_t at91_mci_irq(int irq, void *devid) 
			pr_debug("MMC: Response direction error\n");

			pr_debug("MMC: Response direction error\n");

		if (int_status & AT91_MCI_RINDE)

		if (int_status & AT91_MCI_RINDE)

			pr_debug("MMC: Response index error\n");

			pr_debug("MMC: Response index error\n");



	} else {

		/* Only continue processing if no errors */

		/* Only continue processing if no errors */

	if (!completed) {



		if (int_status & AT91_MCI_TXBUFE) {

		if (int_status & AT91_MCI_TXBUFE) {

			pr_debug("TX buffer empty\n");

			pr_debug("TX buffer empty\n");

			at91_mci_handle_transmitted(host);

			at91_mci_handle_transmitted(host);
@@ -695,9 +698,8 @@ static irqreturn_t at91_mci_irq(int irq, void *devid) 
			at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);

			at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);

		}

		}





		if (int_status & AT91_MCI_ENDTX) {

		if (int_status & AT91_MCI_ENDTX)

			pr_debug("Transmit has ended\n");

			pr_debug("Transmit has ended\n");

		}





		if (int_status & AT91_MCI_ENDRX) {

		if (int_status & AT91_MCI_ENDRX) {

			pr_debug("Receive has ended\n");

			pr_debug("Receive has ended\n");
@@ -709,34 +711,30 @@ static irqreturn_t at91_mci_irq(int irq, void *devid) 
			at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);

			at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);

		}

		}





		if (int_status & AT91_MCI_DTIP) {

		if (int_status & AT91_MCI_DTIP)

			pr_debug("Data transfer in progress\n");

			pr_debug("Data transfer in progress\n");

		}





		if (int_status & AT91_MCI_BLKE) {

		if (int_status & AT91_MCI_BLKE)

			pr_debug("Block transfer has ended\n");

			pr_debug("Block transfer has ended\n");

		}





		if (int_status & AT91_MCI_TXRDY) {

		if (int_status & AT91_MCI_TXRDY)

			pr_debug("Ready to transmit\n");

			pr_debug("Ready to transmit\n");

		}





		if (int_status & AT91_MCI_RXRDY) {

		if (int_status & AT91_MCI_RXRDY)

			pr_debug("Ready to receive\n");

			pr_debug("Ready to receive\n");

		}





		if (int_status & AT91_MCI_CMDRDY) {

		if (int_status & AT91_MCI_CMDRDY) {

			pr_debug("Command ready\n");

			pr_debug("Command ready\n");

			completed = 1;

			completed = 1;

		}

		}

	}

	}

	at91_mci_write(host, AT91_MCI_IDR, int_status);





	if (completed) {

	if (completed) {

		pr_debug("Completed command\n");

		pr_debug("Completed command\n");

		at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);

		at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);

		at91mci_completed_command(host);

		at91mci_completed_command(host);

	}

	} else

		at91_mci_write(host, AT91_MCI_IDR, int_status);





	return IRQ_HANDLED;

	return IRQ_HANDLED;

}

}