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Commit dd95f1a4 authored by Dave Hansen's avatar Dave Hansen Committed by Ingo Molnar
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x86/mm: Put MMU to hardware ASID translation in one place 



There are effectively two ASID types:

 1. The one stored in the mmu_context that goes from 0..5
 2. The one programmed into the hardware that goes from 1..6

This consolidates the locations where converting between the two (by doing
a +1) to a single place which gives us a nice place to comment.
PAGE_TABLE_ISOLATION will also need to, given an ASID, know which hardware
ASID to flush for the userspace mapping.

Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: David Laight <David.Laight@aculab.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Eduardo Valentin <eduval@amazon.com>
Cc: Greg KH <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: aliguori@amazon.com
Cc: daniel.gruss@iaik.tugraz.at
Cc: hughd@google.com
Cc: keescook@google.com
Cc: linux-mm@kvack.org
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent cb0a9144

arch/x86/include/asm/tlbflush.h

+18 −11
Original line number Diff line number Diff line
@@ -85,20 +85,26 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) 
 */

#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_ASID_BITS) - 2)



static inline u16 kern_pcid(u16 asid)

{

	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);

	/*

 * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID bits.

 * This serves two purposes.  It prevents a nasty situation in which

 * PCID-unaware code saves CR3, loads some other value (with PCID == 0),

 * and then restores CR3, thus corrupting the TLB for ASID 0 if the saved

 * ASID was nonzero.  It also means that any bugs involving loading a

 * PCID-enabled CR3 with CR4.PCIDE off will trigger deterministically.

	 * If PCID is on, ASID-aware code paths put the ASID+1 into the

	 * PCID bits.  This serves two purposes.  It prevents a nasty

	 * situation in which PCID-unaware code saves CR3, loads some other

	 * value (with PCID == 0), and then restores CR3, thus corrupting

	 * the TLB for ASID 0 if the saved ASID was nonzero.  It also means

	 * that any bugs involving loading a PCID-enabled CR3 with

	 * CR4.PCIDE off will trigger deterministically.

	 */

	return asid + 1;

}



struct pgd_t;

static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)

{

	if (static_cpu_has(X86_FEATURE_PCID)) {

		VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);

		return __sme_pa(pgd) | (asid + 1);

		return __sme_pa(pgd) | kern_pcid(asid);

	} else {

		VM_WARN_ON_ONCE(asid != 0);

		return __sme_pa(pgd);
@@ -108,7 +114,8 @@ static inline unsigned long build_cr3(pgd_t *pgd, u16 asid) 
static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)

{

	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);

	return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;

	VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID));

	return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;

}



#ifdef CONFIG_PARAVIRT