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Commit dd92d8de authored by Daniel Vetter's avatar Daniel Vetter
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Partially revert "drm/i915: s/mdelay/msleep/" in ilk rps code 



This reverts commit 6adfb1ef.

Ironlake RPS code runs under an irqsave spinlock and hence sleeping
isn't allowed. Not a this long delay while blocking irqs isn't great
at all, but fixing the locking scheme is a lot more involved.

So just revert for now.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: default avatarkernel test robot <ying.huang@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
parent e0548f19

drivers/gpu/drm/i915/intel_pm.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -4266,7 +4266,7 @@ static void ironlake_enable_drps(struct drm_device *dev) 




	if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))

	if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))

		DRM_ERROR("stuck trying to change perf mode\n");

		DRM_ERROR("stuck trying to change perf mode\n");

	msleep(1);

	mdelay(1);





	ironlake_set_drps(dev, fstart);

	ironlake_set_drps(dev, fstart);
@@ -4297,10 +4297,10 @@ static void ironlake_disable_drps(struct drm_device *dev) 




	/* Go back to the starting frequency */

	/* Go back to the starting frequency */

	ironlake_set_drps(dev, dev_priv->ips.fstart);

	ironlake_set_drps(dev, dev_priv->ips.fstart);

	msleep(1);

	mdelay(1);

	rgvswctl |= MEMCTL_CMD_STS;

	rgvswctl |= MEMCTL_CMD_STS;

	I915_WRITE(MEMSWCTL, rgvswctl);

	I915_WRITE(MEMSWCTL, rgvswctl);

	msleep(1);

	mdelay(1);





	spin_unlock_irq(&mchdev_lock);

	spin_unlock_irq(&mchdev_lock);

}

}