Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dc917aec authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'marvell10g-phy-updates' 



Russell King says:

====================
marvell10g updates

This series:
- adds MDI/MDIX reporting
- adds support for 10/100Mbps half-duplex link modes
- adds a comment describing the setup on VF610 ZII boards (where
  the phy interface mode doesn't change.)
- cleans up the phy interace mode switching
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 3abbcccc 6798d03c

drivers/net/phy/marvell10g.c

+69 −41
Original line number Original line Diff line number Diff line
@@ -6,12 +6,18 @@ 
 *

 *

 * There appears to be several different data paths through the PHY which

 * There appears to be several different data paths through the PHY which

 * are automatically managed by the PHY.  The following has been determined

 * are automatically managed by the PHY.  The following has been determined

 * via observation and experimentation:

 * via observation and experimentation for a setup using single-lane Serdes:

 *

 *

 *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)

 *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)

 *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)

 *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)

 *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber

 *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber

 *

 *

 * With XAUI, observation shows:

 *

 *        XAUI PHYXS -- <appropriate PCS as above>

 *

 * and no switching of the host interface mode occurs.

 *

 * If both the fiber and copper ports are connected, the first to gain

 * If both the fiber and copper ports are connected, the first to gain

 * link takes priority and the other port is completely locked out.

 * link takes priority and the other port is completely locked out.

 */

 */
@@ -23,19 +29,17 @@ enum { 
	MV_PCS_BASE_R		= 0x1000,

	MV_PCS_BASE_R		= 0x1000,

	MV_PCS_1000BASEX	= 0x2000,

	MV_PCS_1000BASEX	= 0x2000,





	MV_PCS_PAIRSWAP		= 0x8182,

	MV_PCS_PAIRSWAP_MASK	= 0x0003,

	MV_PCS_PAIRSWAP_AB	= 0x0002,

	MV_PCS_PAIRSWAP_NONE	= 0x0003,



	/* These registers appear at 0x800X and 0xa00X - the 0xa00X control

	/* These registers appear at 0x800X and 0xa00X - the 0xa00X control

	 * registers appear to set themselves to the 0x800X when AN is

	 * registers appear to set themselves to the 0x800X when AN is

	 * restarted, but status registers appear readable from either.

	 * restarted, but status registers appear readable from either.

	 */

	 */

	MV_AN_CTRL1000		= 0x8000, /* 1000base-T control register */

	MV_AN_CTRL1000		= 0x8000, /* 1000base-T control register */

	MV_AN_STAT1000		= 0x8001, /* 1000base-T status register */

	MV_AN_STAT1000		= 0x8001, /* 1000base-T status register */



	/* This register appears to reflect the copper status */

	MV_AN_RESULT		= 0xa016,

	MV_AN_RESULT_SPD_10	= BIT(12),

	MV_AN_RESULT_SPD_100	= BIT(13),

	MV_AN_RESULT_SPD_1000	= BIT(14),

	MV_AN_RESULT_SPD_10000	= BIT(15),

};

};





static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,

static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
@@ -149,12 +153,18 @@ static int mv3310_config_init(struct phy_device *phydev) 
		if (val & MDIO_PMA_EXTABLE_1000BKX)

		if (val & MDIO_PMA_EXTABLE_1000BKX)

			__set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,

			__set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,

				  supported);

				  supported);

		if (val & MDIO_PMA_EXTABLE_100BTX)

		if (val & MDIO_PMA_EXTABLE_100BTX) {

			__set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,

			__set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,

				  supported);

				  supported);

		if (val & MDIO_PMA_EXTABLE_10BT)

			__set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,

				  supported);

		}

		if (val & MDIO_PMA_EXTABLE_10BT) {

			__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,

			__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,

				  supported);

				  supported);

			__set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,

				  supported);

		}

	}

	}





	if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))

	if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
@@ -174,6 +184,9 @@ static int mv3310_config_aneg(struct phy_device *phydev) 
	u32 advertising;

	u32 advertising;

	int ret;

	int ret;





	/* We don't support manual MDI control */

	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;



	if (phydev->autoneg == AUTONEG_DISABLE) {

	if (phydev->autoneg == AUTONEG_DISABLE) {

		ret = genphy_c45_pma_setup_forced(phydev);

		ret = genphy_c45_pma_setup_forced(phydev);

		if (ret < 0)

		if (ret < 0)
@@ -232,6 +245,24 @@ static int mv3310_aneg_done(struct phy_device *phydev) 
	return genphy_c45_aneg_done(phydev);

	return genphy_c45_aneg_done(phydev);

}

}





static void mv3310_update_interface(struct phy_device *phydev)

{

	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||

	     phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {

		/* The PHY automatically switches its serdes interface (and

		 * active PHYXS instance) between Cisco SGMII and 10GBase-KR

		 * modes according to the speed.  Florian suggests setting

		 * phydev->interface to communicate this to the MAC. Only do

		 * this if we are already in either SGMII or 10GBase-KR mode.

		 */

		if (phydev->speed == SPEED_10000)

			phydev->interface = PHY_INTERFACE_MODE_10GKR;

		else if (phydev->speed >= SPEED_10 &&

			 phydev->speed < SPEED_10000)

			phydev->interface = PHY_INTERFACE_MODE_SGMII;

	}

}



/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */

/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */

static int mv3310_read_10gbr_status(struct phy_device *phydev)

static int mv3310_read_10gbr_status(struct phy_device *phydev)

{

{
@@ -239,8 +270,7 @@ static int mv3310_read_10gbr_status(struct phy_device *phydev) 
	phydev->speed = SPEED_10000;

	phydev->speed = SPEED_10000;

	phydev->duplex = DUPLEX_FULL;

	phydev->duplex = DUPLEX_FULL;





	if (phydev->interface == PHY_INTERFACE_MODE_SGMII)

	mv3310_update_interface(phydev);

		phydev->interface = PHY_INTERFACE_MODE_10GKR;





	return 0;

	return 0;

}

}
@@ -263,6 +293,7 @@ static int mv3310_read_status(struct phy_device *phydev) 
	phydev->link = 0;

	phydev->link = 0;

	phydev->pause = 0;

	phydev->pause = 0;

	phydev->asym_pause = 0;

	phydev->asym_pause = 0;

	phydev->mdix = 0;





	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);

	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);

	if (val < 0)

	if (val < 0)
@@ -293,22 +324,8 @@ static int mv3310_read_status(struct phy_device *phydev) 




		phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);

		phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);





		if (phydev->autoneg == AUTONEG_ENABLE) {

		if (phydev->autoneg == AUTONEG_ENABLE)

			val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_RESULT);

			phy_resolve_aneg_linkmode(phydev);

			if (val < 0)

				return val;



			if (val & MV_AN_RESULT_SPD_10000)

				phydev->speed = SPEED_10000;

			else if (val & MV_AN_RESULT_SPD_1000)

				phydev->speed = SPEED_1000;

			else if (val & MV_AN_RESULT_SPD_100)

				phydev->speed = SPEED_100;

			else if (val & MV_AN_RESULT_SPD_10)

				phydev->speed = SPEED_10;



			phydev->duplex = DUPLEX_FULL;

		}

	}

	}





	if (phydev->autoneg != AUTONEG_ENABLE) {

	if (phydev->autoneg != AUTONEG_ENABLE) {
@@ -317,21 +334,30 @@ static int mv3310_read_status(struct phy_device *phydev) 
			return val;

			return val;

	}

	}





	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||

	if (phydev->speed == SPEED_10000) {

	     phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {

		val = genphy_c45_read_mdix(phydev);

		/* The PHY automatically switches its serdes interface (and

		if (val < 0)

		 * active PHYXS instance) between Cisco SGMII and 10GBase-KR

			return val;

		 * modes according to the speed.  Florian suggests setting

	} else {

		 * phydev->interface to communicate this to the MAC. Only do

		val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);

		 * this if we are already in either SGMII or 10GBase-KR mode.

		if (val < 0)

		 */

			return val;

		if (phydev->speed == SPEED_10000)



			phydev->interface = PHY_INTERFACE_MODE_10GKR;

		switch (val & MV_PCS_PAIRSWAP_MASK) {

		else if (phydev->speed >= SPEED_10 &&

		case MV_PCS_PAIRSWAP_AB:

			 phydev->speed < SPEED_10000)

			phydev->mdix = ETH_TP_MDI_X;

			phydev->interface = PHY_INTERFACE_MODE_SGMII;

			break;

		case MV_PCS_PAIRSWAP_NONE:

			phydev->mdix = ETH_TP_MDI;

			break;

		default:

			phydev->mdix = ETH_TP_MDI_INVALID;

			break;

		}

	}

	}





	mv3310_update_interface(phydev);



	return 0;

	return 0;

}

}
@@ -341,7 +367,9 @@ static struct phy_driver mv3310_drivers[] = { 
		.phy_id_mask	= MARVELL_PHY_ID_MASK,

		.phy_id_mask	= MARVELL_PHY_ID_MASK,

		.name		= "mv88x3310",

		.name		= "mv88x3310",

		.features	= SUPPORTED_10baseT_Full |

		.features	= SUPPORTED_10baseT_Full |

				  SUPPORTED_10baseT_Half |

				  SUPPORTED_100baseT_Full |

				  SUPPORTED_100baseT_Full |

				  SUPPORTED_100baseT_Half |

				  SUPPORTED_1000baseT_Full |

				  SUPPORTED_1000baseT_Full |

				  SUPPORTED_Autoneg |

				  SUPPORTED_Autoneg |

				  SUPPORTED_TP |

				  SUPPORTED_TP |

drivers/net/phy/phy-c45.c

+33 −0
Original line number Original line Diff line number Diff line
@@ -233,6 +233,39 @@ int genphy_c45_read_pma(struct phy_device *phydev) 
}

}

EXPORT_SYMBOL_GPL(genphy_c45_read_pma);

EXPORT_SYMBOL_GPL(genphy_c45_read_pma);





/**

 * genphy_c45_read_mdix - read mdix status from PMA

 * @phydev: target phy_device struct

 */

int genphy_c45_read_mdix(struct phy_device *phydev)

{

	int val;



	if (phydev->speed == SPEED_10000) {

		val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,

				   MDIO_PMA_10GBT_SWAPPOL);

		if (val < 0)

			return val;



		switch (val) {

		case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:

			phydev->mdix = ETH_TP_MDI;

			break;



		case 0:

			phydev->mdix = ETH_TP_MDI_X;

			break;



		default:

			phydev->mdix = ETH_TP_MDI_INVALID;

			break;

		}

	}



	return 0;

}

EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);



/* The gen10g_* functions are the old Clause 45 stub */

/* The gen10g_* functions are the old Clause 45 stub */





static int gen10g_config_aneg(struct phy_device *phydev)

static int gen10g_config_aneg(struct phy_device *phydev)

drivers/net/phy/phy-core.c

+43 −0
Original line number Original line Diff line number Diff line
@@ -189,6 +189,49 @@ size_t phy_speeds(unsigned int *speeds, size_t size, 
	return count;

	return count;

}

}





/**

 * phy_resolve_aneg_linkmode - resolve the advertisments into phy settings

 * @phydev: The phy_device struct

 *

 * Resolve our and the link partner advertisments into their corresponding

 * speed and duplex. If full duplex was negotiated, extract the pause mode

 * from the link partner mask.

 */

void phy_resolve_aneg_linkmode(struct phy_device *phydev)

{

	u32 common = phydev->lp_advertising & phydev->advertising;



	if (common & ADVERTISED_10000baseT_Full) {

		phydev->speed = SPEED_10000;

		phydev->duplex = DUPLEX_FULL;

	} else if (common & ADVERTISED_1000baseT_Full) {

		phydev->speed = SPEED_1000;

		phydev->duplex = DUPLEX_FULL;

	} else if (common & ADVERTISED_1000baseT_Half) {

		phydev->speed = SPEED_1000;

		phydev->duplex = DUPLEX_HALF;

	} else if (common & ADVERTISED_100baseT_Full) {

		phydev->speed = SPEED_100;

		phydev->duplex = DUPLEX_FULL;

	} else if (common & ADVERTISED_100baseT_Half) {

		phydev->speed = SPEED_100;

		phydev->duplex = DUPLEX_HALF;

	} else if (common & ADVERTISED_10baseT_Full) {

		phydev->speed = SPEED_10;

		phydev->duplex = DUPLEX_FULL;

	} else if (common & ADVERTISED_10baseT_Half) {

		phydev->speed = SPEED_10;

		phydev->duplex = DUPLEX_HALF;

	}



	if (phydev->duplex == DUPLEX_FULL) {

		phydev->pause = !!(phydev->lp_advertising & ADVERTISED_Pause);

		phydev->asym_pause = !!(phydev->lp_advertising &

					ADVERTISED_Asym_Pause);

	}

}

EXPORT_SYMBOL_GPL(phy_resolve_aneg_linkmode);



static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,

static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,

			     u16 regnum)

			     u16 regnum)

{

{

include/linux/phy.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -690,6 +690,8 @@ phy_lookup_setting(int speed, int duplex, const unsigned long *mask, 
size_t phy_speeds(unsigned int *speeds, size_t size,

size_t phy_speeds(unsigned int *speeds, size_t size,

		  unsigned long *mask, size_t maxbit);

		  unsigned long *mask, size_t maxbit);





void phy_resolve_aneg_linkmode(struct phy_device *phydev);



/**

/**

 * phy_read_mmd - Convenience function for reading a register

 * phy_read_mmd - Convenience function for reading a register

 * from an MMD on a given PHY.

 * from an MMD on a given PHY.
@@ -901,6 +903,7 @@ int genphy_c45_read_lpa(struct phy_device *phydev); 
int genphy_c45_read_pma(struct phy_device *phydev);

int genphy_c45_read_pma(struct phy_device *phydev);

int genphy_c45_pma_setup_forced(struct phy_device *phydev);

int genphy_c45_pma_setup_forced(struct phy_device *phydev);

int genphy_c45_an_disable_aneg(struct phy_device *phydev);

int genphy_c45_an_disable_aneg(struct phy_device *phydev);

int genphy_c45_read_mdix(struct phy_device *phydev);





static inline int phy_read_status(struct phy_device *phydev)

static inline int phy_read_status(struct phy_device *phydev)

{

{