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Commit dc8d5f8d authored by Russell King's avatar Russell King
Browse files

dmaengine: PL08x: get rid of unnecessary checks in dma_slave_config 



Get rid of the unnecessary checks in dma_slave_config utilizing
the DMA direction.  This allows us to move the computation of
cctl to the prepare function.

Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Tested-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 800d683e

arch/arm/mach-spear3xx/spear300.c

+0 −26
Original line number Diff line number Diff line
@@ -120,182 +120,156 @@ struct pl08x_channel_data spear300_dma_info[] = { 
		.min_signal = 2,

		.max_signal = 2,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart0_tx",

		.min_signal = 3,

		.max_signal = 3,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp0_rx",

		.min_signal = 8,

		.max_signal = 8,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp0_tx",

		.min_signal = 9,

		.max_signal = 9,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "i2c_rx",

		.min_signal = 10,

		.max_signal = 10,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "i2c_tx",

		.min_signal = 11,

		.max_signal = 11,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "irda",

		.min_signal = 12,

		.max_signal = 12,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "adc",

		.min_signal = 13,

		.max_signal = 13,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "to_jpeg",

		.min_signal = 14,

		.max_signal = 14,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "from_jpeg",

		.min_signal = 15,

		.max_signal = 15,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras0_rx",

		.min_signal = 0,

		.max_signal = 0,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras0_tx",

		.min_signal = 1,

		.max_signal = 1,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras1_rx",

		.min_signal = 2,

		.max_signal = 2,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras1_tx",

		.min_signal = 3,

		.max_signal = 3,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras2_rx",

		.min_signal = 4,

		.max_signal = 4,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras2_tx",

		.min_signal = 5,

		.max_signal = 5,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras3_rx",

		.min_signal = 6,

		.max_signal = 6,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras3_tx",

		.min_signal = 7,

		.max_signal = 7,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras4_rx",

		.min_signal = 8,

		.max_signal = 8,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras4_tx",

		.min_signal = 9,

		.max_signal = 9,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras5_rx",

		.min_signal = 10,

		.max_signal = 10,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras5_tx",

		.min_signal = 11,

		.max_signal = 11,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras6_rx",

		.min_signal = 12,

		.max_signal = 12,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras6_tx",

		.min_signal = 13,

		.max_signal = 13,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras7_rx",

		.min_signal = 14,

		.max_signal = 14,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras7_tx",

		.min_signal = 15,

		.max_signal = 15,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	},

};

arch/arm/mach-spear3xx/spear310.c

+0 −26
Original line number Diff line number Diff line
@@ -205,182 +205,156 @@ struct pl08x_channel_data spear310_dma_info[] = { 
		.min_signal = 2,

		.max_signal = 2,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart0_tx",

		.min_signal = 3,

		.max_signal = 3,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp0_rx",

		.min_signal = 8,

		.max_signal = 8,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp0_tx",

		.min_signal = 9,

		.max_signal = 9,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "i2c_rx",

		.min_signal = 10,

		.max_signal = 10,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "i2c_tx",

		.min_signal = 11,

		.max_signal = 11,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "irda",

		.min_signal = 12,

		.max_signal = 12,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "adc",

		.min_signal = 13,

		.max_signal = 13,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "to_jpeg",

		.min_signal = 14,

		.max_signal = 14,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "from_jpeg",

		.min_signal = 15,

		.max_signal = 15,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart1_rx",

		.min_signal = 0,

		.max_signal = 0,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart1_tx",

		.min_signal = 1,

		.max_signal = 1,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart2_rx",

		.min_signal = 2,

		.max_signal = 2,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart2_tx",

		.min_signal = 3,

		.max_signal = 3,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart3_rx",

		.min_signal = 4,

		.max_signal = 4,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart3_tx",

		.min_signal = 5,

		.max_signal = 5,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart4_rx",

		.min_signal = 6,

		.max_signal = 6,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart4_tx",

		.min_signal = 7,

		.max_signal = 7,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart5_rx",

		.min_signal = 8,

		.max_signal = 8,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart5_tx",

		.min_signal = 9,

		.max_signal = 9,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras5_rx",

		.min_signal = 10,

		.max_signal = 10,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras5_tx",

		.min_signal = 11,

		.max_signal = 11,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras6_rx",

		.min_signal = 12,

		.max_signal = 12,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras6_tx",

		.min_signal = 13,

		.max_signal = 13,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras7_rx",

		.min_signal = 14,

		.max_signal = 14,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras7_tx",

		.min_signal = 15,

		.max_signal = 15,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	},

};

arch/arm/mach-spear3xx/spear320.c

+0 −26
Original line number Diff line number Diff line
@@ -213,182 +213,156 @@ struct pl08x_channel_data spear320_dma_info[] = { 
		.min_signal = 2,

		.max_signal = 2,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart0_tx",

		.min_signal = 3,

		.max_signal = 3,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp0_rx",

		.min_signal = 8,

		.max_signal = 8,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp0_tx",

		.min_signal = 9,

		.max_signal = 9,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "i2c0_rx",

		.min_signal = 10,

		.max_signal = 10,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "i2c0_tx",

		.min_signal = 11,

		.max_signal = 11,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "irda",

		.min_signal = 12,

		.max_signal = 12,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "adc",

		.min_signal = 13,

		.max_signal = 13,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "to_jpeg",

		.min_signal = 14,

		.max_signal = 14,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "from_jpeg",

		.min_signal = 15,

		.max_signal = 15,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp1_rx",

		.min_signal = 0,

		.max_signal = 0,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ssp1_tx",

		.min_signal = 1,

		.max_signal = 1,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ssp2_rx",

		.min_signal = 2,

		.max_signal = 2,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ssp2_tx",

		.min_signal = 3,

		.max_signal = 3,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "uart1_rx",

		.min_signal = 4,

		.max_signal = 4,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "uart1_tx",

		.min_signal = 5,

		.max_signal = 5,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "uart2_rx",

		.min_signal = 6,

		.max_signal = 6,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "uart2_tx",

		.min_signal = 7,

		.max_signal = 7,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "i2c1_rx",

		.min_signal = 8,

		.max_signal = 8,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "i2c1_tx",

		.min_signal = 9,

		.max_signal = 9,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "i2c2_rx",

		.min_signal = 10,

		.max_signal = 10,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "i2c2_tx",

		.min_signal = 11,

		.max_signal = 11,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "i2s_rx",

		.min_signal = 12,

		.max_signal = 12,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "i2s_tx",

		.min_signal = 13,

		.max_signal = 13,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "rs485_rx",

		.min_signal = 14,

		.max_signal = 14,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "rs485_tx",

		.min_signal = 15,

		.max_signal = 15,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	},

};

arch/arm/mach-spear3xx/spear3xx.c

+2 −1
Original line number Diff line number Diff line
@@ -46,7 +46,8 @@ struct pl022_ssp_controller pl022_plat_data = { 
struct pl08x_platform_data pl080_plat_data = {

	.memcpy_channel = {

		.bus_id = "memcpy",

		.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \

		.cctl_memcpy =

			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \

			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \

			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \

			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \

arch/arm/mach-spear6xx/spear6xx.c

+2 −49
Original line number Diff line number Diff line
@@ -36,336 +36,288 @@ static struct pl08x_channel_data spear600_dma_info[] = { 
		.min_signal = 0,

		.max_signal = 0,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp1_tx",

		.min_signal = 1,

		.max_signal = 1,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart0_rx",

		.min_signal = 2,

		.max_signal = 2,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart0_tx",

		.min_signal = 3,

		.max_signal = 3,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart1_rx",

		.min_signal = 4,

		.max_signal = 4,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "uart1_tx",

		.min_signal = 5,

		.max_signal = 5,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp2_rx",

		.min_signal = 6,

		.max_signal = 6,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ssp2_tx",

		.min_signal = 7,

		.max_signal = 7,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ssp0_rx",

		.min_signal = 8,

		.max_signal = 8,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ssp0_tx",

		.min_signal = 9,

		.max_signal = 9,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "i2c_rx",

		.min_signal = 10,

		.max_signal = 10,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "i2c_tx",

		.min_signal = 11,

		.max_signal = 11,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "irda",

		.min_signal = 12,

		.max_signal = 12,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "adc",

		.min_signal = 13,

		.max_signal = 13,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "to_jpeg",

		.min_signal = 14,

		.max_signal = 14,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "from_jpeg",

		.min_signal = 15,

		.max_signal = 15,

		.muxval = 0,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras0_rx",

		.min_signal = 0,

		.max_signal = 0,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras0_tx",

		.min_signal = 1,

		.max_signal = 1,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras1_rx",

		.min_signal = 2,

		.max_signal = 2,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras1_tx",

		.min_signal = 3,

		.max_signal = 3,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras2_rx",

		.min_signal = 4,

		.max_signal = 4,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras2_tx",

		.min_signal = 5,

		.max_signal = 5,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras3_rx",

		.min_signal = 6,

		.max_signal = 6,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras3_tx",

		.min_signal = 7,

		.max_signal = 7,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras4_rx",

		.min_signal = 8,

		.max_signal = 8,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras4_tx",

		.min_signal = 9,

		.max_signal = 9,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras5_rx",

		.min_signal = 10,

		.max_signal = 10,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras5_tx",

		.min_signal = 11,

		.max_signal = 11,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras6_rx",

		.min_signal = 12,

		.max_signal = 12,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras6_tx",

		.min_signal = 13,

		.max_signal = 13,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras7_rx",

		.min_signal = 14,

		.max_signal = 14,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ras7_tx",

		.min_signal = 15,

		.max_signal = 15,

		.muxval = 1,

		.cctl = 0,

		.periph_buses = PL08X_AHB1,

	}, {

		.bus_id = "ext0_rx",

		.min_signal = 0,

		.max_signal = 0,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext0_tx",

		.min_signal = 1,

		.max_signal = 1,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext1_rx",

		.min_signal = 2,

		.max_signal = 2,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext1_tx",

		.min_signal = 3,

		.max_signal = 3,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext2_rx",

		.min_signal = 4,

		.max_signal = 4,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext2_tx",

		.min_signal = 5,

		.max_signal = 5,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext3_rx",

		.min_signal = 6,

		.max_signal = 6,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext3_tx",

		.min_signal = 7,

		.max_signal = 7,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext4_rx",

		.min_signal = 8,

		.max_signal = 8,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext4_tx",

		.min_signal = 9,

		.max_signal = 9,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext5_rx",

		.min_signal = 10,

		.max_signal = 10,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext5_tx",

		.min_signal = 11,

		.max_signal = 11,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext6_rx",

		.min_signal = 12,

		.max_signal = 12,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext6_tx",

		.min_signal = 13,

		.max_signal = 13,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext7_rx",

		.min_signal = 14,

		.max_signal = 14,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	}, {

		.bus_id = "ext7_tx",

		.min_signal = 15,

		.max_signal = 15,

		.muxval = 2,

		.cctl = 0,

		.periph_buses = PL08X_AHB2,

	},

};
@@ -373,7 +325,8 @@ static struct pl08x_channel_data spear600_dma_info[] = { 
struct pl08x_platform_data pl080_plat_data = {

	.memcpy_channel = {

		.bus_id = "memcpy",

		.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \

		.cctl_memcpy =

			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \

			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \

			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \

			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \