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Commit db8feb69 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-2016-11-08' of git://anongit.freedesktop.org/git/drm-intel into drm-next 

- gpu idling rework for s/r (Imre)
- vlv mappable scanout fix
- speed up probing in resume (Lyude)
- dp audio workarounds for gen9 (Dhinakaran)
- more conversion to using dev_priv internally (Ville)
- more gen9+ wm fixes and cleanups (Maarten)
- shrinker cleanup&fixes (Chris)
- reorg plane init code (Ville)
- implement support for multiple timelines (prep work for scheduler)
  from Chris and all
- untangle dev->struct_mutex locking as prep for multiple timelines
  (Chris)
- refactor bxt phy code and collect it all in intel_dpio_phy.c (Ander)
- another gvt with bugfixes all over from Zhenyu
- piles of lspcon fixes from Imre
- 90/270 rotation fixes (Ville)
- guc log buffer support (Akash+Sagar)
- fbc fixes from Paulo
- untangle rpm vs. tiling-fences/mmaps (Chris)
- fix atomic commit to wait on the right fences (Daniel Stone)

* tag 'drm-intel-next-2016-11-08' of git://anongit.freedesktop.org/git/drm-intel: (181 commits)
  drm/i915: Update DRIVER_DATE to 20161108
  drm/i915: Mark CPU cache as dirty when used for rendering
  drm/i915: Add assert for no pending GPU requests during suspend/resume in LR mode
  drm/i915: Make sure engines are idle during GPU idling in LR mode
  drm/i915: Avoid early GPU idling due to race with new request
  drm/i915: Avoid early GPU idling due to already pending idle work
  drm/i915: Limit Valleyview and earlier to only using mappable scanout
  drm/i915: Round tile chunks up for constructing partial VMAs
  drm/i915: Remove the vma from the object list upon close
  drm/i915: Reinit polling before hpd when resuming
  drm/i915: Remove redundant reprobe in i915_drm_resume
  drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
  drm/i915/dp: BDW cdclk fix for DP audio
  drm/i915: Fix pages pin counting around swizzle quirk
  drm/i915: Fix test on inputs for vma_compare()
  drm/i915/guc: Cache the client mapping
  drm/i915: Tidy slab cache allocations
  drm/i915: Introduce HAS_64BIT_RELOC
  drm/i915: Show the execlist queue in debugfs/i915_engine_info
  drm/i915: Unify global_list into global_link
  ...
parents afdd548f 58e197d6

Documentation/gpu/i915.rst

+1 −1
Original line number Diff line number Diff line
@@ -189,7 +189,7 @@ Display Refresh Rate Switching (DRRS) 
DPIO

----



.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h

.. kernel-doc:: drivers/gpu/drm/i915/intel_dpio_phy.c

   :doc: DPIO



CSR firmware support for DMC

MAINTAINERS

+0 −1
Original line number Diff line number Diff line
@@ -4060,7 +4060,6 @@ INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) 
M:	Daniel Vetter <daniel.vetter@intel.com>

M:	Jani Nikula <jani.nikula@linux.intel.com>

L:	intel-gfx@lists.freedesktop.org

L:	dri-devel@lists.freedesktop.org

W:	https://01.org/linuxgraphics/

Q:	http://patchwork.freedesktop.org/project/intel-gfx/

T:	git git://anongit.freedesktop.org/drm-intel

drivers/gpu/drm/i915/Kconfig

+8 −5
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ config DRM_I915 
	select DRM_KMS_HELPER

	select DRM_PANEL

	select DRM_MIPI_DSI

	select RELAY

	# i915 depends on ACPI_VIDEO when ACPI is enabled

	# but for select to work, need to select ACPI_VIDEO's dependencies, ick

	select BACKLIGHT_LCD_SUPPORT if ACPI
@@ -24,16 +25,17 @@ config DRM_I915 
	  including 830M, 845G, 852GM, 855GM, 865G, 915G, 945G, 965G,

	  G35, G41, G43, G45 chipsets and Celeron, Pentium, Core i3,

	  Core i5, Core i7 as well as Atom CPUs with integrated graphics.

	  If M is selected, the module will be called i915.  AGP support

	  is required for this driver to work. This driver is used by

	  the Intel driver in X.org 6.8 and XFree86 4.4 and above. It

	  replaces the older i830 module that supported a subset of the

	  hardware in older X.org releases.



	  This driver is used by the Intel driver in X.org 6.8 and

	  XFree86 4.4 and above. It replaces the older i830 module that

	  supported a subset of the hardware in older X.org releases.



	  Note that the older i810/i815 chipsets require the use of the

	  i810 driver instead, and the Atom z5xx series has an entirely

	  different implementation.



	  If "M" is selected, the module will be called i915.



config DRM_I915_PRELIMINARY_HW_SUPPORT

	bool "Enable preliminary support for prerelease Intel hardware by default"

	depends on DRM_I915
@@ -85,6 +87,7 @@ config DRM_I915_USERPTR 
config DRM_I915_GVT

        bool "Enable Intel GVT-g graphics virtualization host support"

        depends on DRM_I915

        depends on 64BIT

        default n

        help

	  Choose this option if you want to enable Intel GVT-g graphics

drivers/gpu/drm/i915/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -35,16 +35,19 @@ i915-y += i915_cmd_parser.o \ 
	  i915_gem_execbuffer.o \

	  i915_gem_fence.o \

	  i915_gem_gtt.o \

	  i915_gem_internal.o \

	  i915_gem.o \

	  i915_gem_render_state.o \

	  i915_gem_request.o \

	  i915_gem_shrinker.o \

	  i915_gem_stolen.o \

	  i915_gem_tiling.o \

	  i915_gem_timeline.o \

	  i915_gem_userptr.o \

	  i915_trace_points.o \

	  intel_breadcrumbs.o \

	  intel_engine_cs.o \

	  intel_hangcheck.o \

	  intel_lrc.o \

	  intel_mocs.o \

	  intel_ringbuffer.o \

drivers/gpu/drm/i915/gvt/cmd_parser.c

+14 −15
Original line number Diff line number Diff line
@@ -1145,7 +1145,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, 
		info->event = PRIMARY_B_FLIP_DONE;

		break;

	case MI_DISPLAY_FLIP_SKL_PLANE_1_C:

		info->pipe = PIPE_B;

		info->pipe = PIPE_C;

		info->event = PRIMARY_C_FLIP_DONE;

		break;

	default:
@@ -1201,20 +1201,19 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 
	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;

	struct intel_vgpu *vgpu = s->vgpu;



#define write_bits(reg, e, s, v) do { \

	vgpu_vreg(vgpu, reg) &= ~GENMASK(e, s); \

	vgpu_vreg(vgpu, reg) |= (v << s); \

} while (0)



	write_bits(info->surf_reg, 31, 12, info->surf_val);

	if (IS_SKYLAKE(dev_priv))

		write_bits(info->stride_reg, 9, 0, info->stride_val);

	else

		write_bits(info->stride_reg, 15, 6, info->stride_val);

	write_bits(info->ctrl_reg, IS_SKYLAKE(dev_priv) ? 12 : 10,

		   10, info->tile_val);



#undef write_bits

	set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (IS_SKYLAKE(dev_priv)) {

		set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),

			      info->tile_val << 10);

	} else {

		set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(15, 6),

			      info->stride_val << 6);

		set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(10, 10),

			      info->tile_val << 10);

	}



	vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;

	intel_vgpu_trigger_virtual_event(vgpu, info->event);