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Commit db5b0ae0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC device tree conversions and enablement from Olof Johansson:
 "Continued device tree conversion and enablement across a number of
  platforms; Kirkwood, tegra, i.MX, Exynos, zynq and a couple of other
  smaller series as well.

  ux500 has seen continued conversion for platforms.  Several platforms
  have seen pinctrl-via-devicetree conversions for simpler
  multiplatform.  Tegra is adding data for new devices/drivers, and
  Exynos has a bunch of new bindings and devices added as well.

  So, pretty much the same progression in the right direction as the
  last few releases."

Fix up conflicts as per Olof.

* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (185 commits)
  ARM: ux500: Rename dbx500 cpufreq code to be more generic
  ARM: dts: add missing ux500 device trees
  ARM: ux500: Stop registering the PCM driver from platform code
  ARM: ux500: Move board specific GPIO info out to subordinate DTS files
  ARM: ux500: Disable the MMCI gpio-regulator by default
  ARM: Kirkwood: remove kirkwood_ehci_init() from new boards
  ARM: Kirkwood: Add support LED of OpenBlocks A6
  ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6
  ARM: kirkwood: Add NAND partiton map for OpenBlocks A6
  ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6
  ARM: kirkwood: Add support DT of second I2C bus
  ARM: kirkwood: Convert mplcec4 board to pinctrl
  ARM: Kirkwood: Convert km_kirkwood to pinctrl
  ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl
  ARM: Kirkwood: Convert IX2-200 to pinctrl.
  ARM: Kirkwood: Convert lsxl boards to pinctrl.
  ARM: Kirkwood: Convert ib62x0 to pinctrl.
  ARM: Kirkwood: Convert GoFlex Net to pinctrl.
  ARM: Kirkwood: Convert dreamplug to pinctrl.
  ARM: Kirkwood: Convert dockstar to pinctrl.
  ...
parents 6be35c70 64507dd7

Documentation/devicetree/bindings/arm/exynos/power_domain.txt

+11 −4
Original line number Diff line number Diff line
@@ -4,14 +4,13 @@ Exynos processors include support for multiple power domains which are used 
to gate power to one or more peripherals on the processor.



Required Properties:

- compatiable: should be one of the following.

- compatible: should be one of the following.

    * samsung,exynos4210-pd - for exynos4210 type power domain.

- reg: physical base address of the controller and length of memory mapped

    region.



Optional Properties:

- samsung,exynos4210-pd-off: Specifies that the power domain is in turned-off

    state during boot and remains to be turned-off until explicitly turned-on.

Node of a device using power domains must have a samsung,power-domain property

defined with a phandle to respective power domain.



Example:
@@ -19,3 +18,11 @@ Example: 
		compatible = "samsung,exynos4210-pd";

		reg = <0x10023C00 0x10>;

	};



Example of the node using power domain:



	node {

		/* ... */

		samsung,power-domain = <&lcd0>;

		/* ... */

	};

Documentation/devicetree/bindings/arm/fsl.txt

+4 −0
Original line number Diff line number Diff line
@@ -41,6 +41,10 @@ i.MX6 Quad SABRE Smart Device Board 
Required root node properties:

    - compatible = "fsl,imx6q-sabresd", "fsl,imx6q";



i.MX6 Quad SABRE Automotive Board

Required root node properties:

    - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";



Generic i.MX boards

-------------------

Documentation/devicetree/bindings/ata/exynos-sata-phy.txt

0 → 100644
+14 −0
Original line number Diff line number Diff line 
* Samsung SATA PHY Controller



SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.

Each SATA PHY controller should have its own node.



Required properties:

- compatible        : compatible list, contains "samsung,exynos5-sata-phy"

- reg               : <registers mapping>



Example:

        sata@ffe07000 {

                compatible = "samsung,exynos5-sata-phy";

                reg = <0xffe07000 0x1000>;

        };

Documentation/devicetree/bindings/ata/exynos-sata.txt

0 → 100644
+17 −0
Original line number Diff line number Diff line 
* Samsung AHCI SATA Controller



SATA nodes are defined to describe on-chip Serial ATA controllers.

Each SATA controller should have its own node.



Required properties:

- compatible        : compatible list, contains "samsung,exynos5-sata"

- interrupts        : <interrupt mapping for SATA IRQ>

- reg               : <registers mapping>

- samsung,sata-freq : <frequency in MHz>



Example:

        sata@ffe08000 {

                compatible = "samsung,exynos5-sata";

                reg = <0xffe08000 0x1000>;

                interrupts = <115>;

        };

Documentation/devicetree/bindings/clock/imx25-clock.txt

0 → 100644
+162 −0
Original line number Diff line number Diff line 
* Clock bindings for Freescale i.MX25



Required properties:

- compatible: Should be "fsl,imx25-ccm"

- reg: Address and length of the register set

- interrupts: Should contain CCM interrupt

- #clock-cells: Should be <1>



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX25

clocks and IDs.



	Clock			ID

	---------------------------

	dummy			0

	osc			1

	mpll			2

	upll			3

	mpll_cpu_3_4		4

	cpu_sel			5

	cpu			6

	ahb			7

	usb_div			8

	ipg			9

	per0_sel		10

	per1_sel		11

	per2_sel		12

	per3_sel		13

	per4_sel		14

	per5_sel		15

	per6_sel		16

	per7_sel		17

	per8_sel		18

	per9_sel		19

	per10_sel		20

	per11_sel		21

	per12_sel		22

	per13_sel		23

	per14_sel		24

	per15_sel		25

	per0			26

	per1			27

	per2			28

	per3			29

	per4			30

	per5			31

	per6			32

	per7			33

	per8			34

	per9			35

	per10			36

	per11			37

	per12			38

	per13			39

	per14			40

	per15			41

	csi_ipg_per		42

	epit_ipg_per		43

	esai_ipg_per		44

	esdhc1_ipg_per		45

	esdhc2_ipg_per		46

	gpt_ipg_per		47

	i2c_ipg_per		48

	lcdc_ipg_per		49

	nfc_ipg_per		50

	owire_ipg_per		51

	pwm_ipg_per		52

	sim1_ipg_per		53

	sim2_ipg_per		54

	ssi1_ipg_per		55

	ssi2_ipg_per		56

	uart_ipg_per		57

	ata_ahb			58

	reserved		59

	csi_ahb			60

	emi_ahb			61

	esai_ahb		62

	esdhc1_ahb		63

	esdhc2_ahb		64

	fec_ahb			65

	lcdc_ahb		66

	rtic_ahb		67

	sdma_ahb		68

	slcdc_ahb		69

	usbotg_ahb		70

	reserved		71

	reserved		72

	reserved		73

	reserved		74

	can1_ipg		75

	can2_ipg		76

	csi_ipg			77

	cspi1_ipg		78

	cspi2_ipg		79

	cspi3_ipg		80

	dryice_ipg		81

	ect_ipg			82

	epit1_ipg		83

	epit2_ipg		84

	reserved		85

	esdhc1_ipg		86

	esdhc2_ipg		87

	fec_ipg			88

	reserved		89

	reserved		90

	reserved		91

	gpt1_ipg		92

	gpt2_ipg		93

	gpt3_ipg		94

	gpt4_ipg		95

	reserved		96

	reserved		97

	reserved		98

	iim_ipg			99

	reserved		100

	reserved		101

	kpp_ipg			102

	lcdc_ipg		103

	reserved		104

	pwm1_ipg		105

	pwm2_ipg		106

	pwm3_ipg		107

	pwm4_ipg		108

	rngb_ipg		109

	reserved		110

	scc_ipg			111

	sdma_ipg		112

	sim1_ipg		113

	sim2_ipg		114

	slcdc_ipg		115

	spba_ipg		116

	ssi1_ipg		117

	ssi2_ipg		118

	tsc_ipg			119

	uart1_ipg		120

	uart2_ipg		121

	uart3_ipg		122

	uart4_ipg		123

	uart5_ipg		124

	reserved		125

	wdt_ipg			126



Examples:



clks: ccm@53f80000 {

	compatible = "fsl,imx25-ccm";

	reg = <0x53f80000 0x4000>;

	interrupts = <31>;

	clock-output-names = ...

			"uart_ipg",

			"uart_serial",

			...;

};



uart1: serial@43f90000 {

	compatible = "fsl,imx25-uart", "fsl,imx21-uart";

	reg = <0x43f90000 0x4000>;

	interrupts = <45>;

	clocks = <&clks 79>, <&clks 50>;

	clock-names = "ipg", "per";

	status = "disabled";

};