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Commit db2ce7f3 authored by Bin Meng's avatar Bin Meng Committed by Cyrille Pitchen
Browse files

spi-nor: intel-spi: Check transfer length in the HW/SW cycle 



Intel SPI controller only has a 64 bytes FIFO. This adds a sanity
check before triggering any HW/SW sequencer work.

Additionally for the SW sequencer, if given data length is zero,
we should not mark the 'Data Cycle' bit.

Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
parent 9d63f176

drivers/mtd/spi-nor/intel-spi.c

+10 −2
Original line number Diff line number Diff line
@@ -399,6 +399,9 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len) 
		return -EINVAL;

	}



	if (len > INTEL_SPI_FIFO_SZ)

		return -EINVAL;



	val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;

	val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;

	val |= HSFSTS_CTL_FGO;
@@ -419,13 +422,18 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len) 


static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len)

{

	u32 val, status;

	u32 val = 0, status;

	int ret;



	ret = intel_spi_opcode_index(ispi, opcode);

	if (ret < 0)

		return ret;



	if (len > INTEL_SPI_FIFO_SZ)

		return -EINVAL;



	/* Only mark 'Data Cycle' bit when there is data to be transferred */

	if (len > 0)

		val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;

	val |= ret << SSFSTS_CTL_COP_SHIFT;

	val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;