drm/nouveau: kill nouveau_dev() + wrap register macros (db2bec18) · Commits · e / devices / android_kernel_teracube_emerald

drivers/gpu/drm/nouveau/dispnv04/arb.c

+4 −4

Original line number	Original line	Diff line number	Diff line
	@@ -198,12 +198,12 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
	int burst, int lwm)		int burst, int lwm)
	{		{
	struct nouveau_drm *drm = nouveau_drm(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_device *device = nouveau_dev(dev);		struct nouveau_object *device = nouveau_drm(dev)->device;
	struct nv_fifo_info fifo_data;		struct nv_fifo_info fifo_data;
	struct nv_sim_state sim_data;		struct nv_sim_state sim_data;
	int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);		int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
	int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);		int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
	uint32_t cfg1 = nv_rd32(device, NV04_PFB_CFG1);		uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);

	sim_data.pclk_khz = VClk;		sim_data.pclk_khz = VClk;
	sim_data.mclk_khz = MClk;		sim_data.mclk_khz = MClk;
	@@ -221,8 +221,8 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
	sim_data.mem_latency = 3;		sim_data.mem_latency = 3;
	sim_data.mem_page_miss = 10;		sim_data.mem_page_miss = 10;
	} else {		} else {
	sim_data.memory_type = nv_rd32(device, NV04_PFB_CFG0) & 0x1;		sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1;
	sim_data.memory_width = (nv_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;		sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
	sim_data.mem_latency = cfg1 & 0xf;		sim_data.mem_latency = cfg1 & 0xf;
	sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);		sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
	}		}

drivers/gpu/drm/nouveau/dispnv04/dac.c

+23 −23

Original line number	Original line	Diff line number	Diff line
	@@ -65,7 +65,7 @@ int nv04_dac_output_offset(struct drm_encoder *encoder)

	static int sample_load_twice(struct drm_device *dev, bool sense[2])		static int sample_load_twice(struct drm_device *dev, bool sense[2])
	{		{
	struct nouveau_device *device = nouveau_dev(dev);		struct nouveau_object *device = nouveau_drm(dev)->device;
	struct nouveau_timer *ptimer = nouveau_timer(device);		struct nouveau_timer *ptimer = nouveau_timer(device);
	int i;		int i;

	@@ -95,15 +95,15 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2])

	udelay(100);		udelay(100);
	/* when level triggers, sense is _LO_ */		/* when level triggers, sense is _LO_ */
	sense_a = nv_rd08(device, NV_PRMCIO_INP0) & 0x10;		sense_a = nvif_rd08(device, NV_PRMCIO_INP0) & 0x10;

	/* take another reading until it agrees with sense_a... */		/* take another reading until it agrees with sense_a... */
	do {		do {
	udelay(100);		udelay(100);
	sense_b = nv_rd08(device, NV_PRMCIO_INP0) & 0x10;		sense_b = nvif_rd08(device, NV_PRMCIO_INP0) & 0x10;
	if (sense_a != sense_b) {		if (sense_a != sense_b) {
	sense_b_prime =		sense_b_prime =
	nv_rd08(device, NV_PRMCIO_INP0) & 0x10;		nvif_rd08(device, NV_PRMCIO_INP0) & 0x10;
	if (sense_b == sense_b_prime) {		if (sense_b == sense_b_prime) {
	/* ... unless two consecutive subsequent		/* ... unless two consecutive subsequent
	* samples agree; sense_a is replaced */		* samples agree; sense_a is replaced */
	@@ -128,7 +128,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
	struct drm_connector *connector)		struct drm_connector *connector)
	{		{
	struct drm_device *dev = encoder->dev;		struct drm_device *dev = encoder->dev;
	struct nouveau_device *device = nouveau_dev(dev);		struct nouveau_object *device = nouveau_drm(dev)->device;
	struct nouveau_drm *drm = nouveau_drm(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;		uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
	uint8_t saved_palette0[3], saved_palette_mask;		uint8_t saved_palette0[3], saved_palette_mask;
	@@ -164,11 +164,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
	saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX);		saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX);
	NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);		NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);

	nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS, 0x0);		nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS, 0x0);
	for (i = 0; i < 3; i++)		for (i = 0; i < 3; i++)
	saved_palette0[i] = nv_rd08(device, NV_PRMDIO_PALETTE_DATA);		saved_palette0[i] = nvif_rd08(device, NV_PRMDIO_PALETTE_DATA);
	saved_palette_mask = nv_rd08(device, NV_PRMDIO_PIXEL_MASK);		saved_palette_mask = nvif_rd08(device, NV_PRMDIO_PIXEL_MASK);
	nv_wr08(device, NV_PRMDIO_PIXEL_MASK, 0);		nvif_wr08(device, NV_PRMDIO_PIXEL_MASK, 0);

	saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL);		saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL);
	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL,		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL,
	@@ -181,11 +181,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
	do {		do {
	bool sense_pair[2];		bool sense_pair[2];

	nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);		nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
	nv_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);		nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);
	nv_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);		nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);
	/* testing blue won't find monochrome monitors. I don't care */		/* testing blue won't find monochrome monitors. I don't care */
	nv_wr08(device, NV_PRMDIO_PALETTE_DATA, blue);		nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, blue);

	i = 0;		i = 0;
	/* take sample pairs until both samples in the pair agree */		/* take sample pairs until both samples in the pair agree */
	@@ -208,11 +208,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
	} while (++blue < 0x18 && sense);		} while (++blue < 0x18 && sense);

	out:		out:
	nv_wr08(device, NV_PRMDIO_PIXEL_MASK, saved_palette_mask);		nvif_wr08(device, NV_PRMDIO_PIXEL_MASK, saved_palette_mask);
	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl);		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl);
	nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);		nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
	for (i = 0; i < 3; i++)		for (i = 0; i < 3; i++)
	nv_wr08(device, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]);		nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]);
	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl);		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl);
	NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);		NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
	NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);		NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
	@@ -231,7 +231,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
	{		{
	struct drm_device *dev = encoder->dev;		struct drm_device *dev = encoder->dev;
	struct nouveau_drm *drm = nouveau_drm(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_device *device = nouveau_dev(dev);		struct nouveau_object *device = nouveau_drm(dev)->device;
	struct nouveau_gpio *gpio = nouveau_gpio(device);		struct nouveau_gpio *gpio = nouveau_gpio(device);
	struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;		struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
	uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);		uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
	@@ -256,12 +256,12 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,
	saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);		saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);

	saved_powerctrl_2 = nv_rd32(device, NV_PBUS_POWERCTRL_2);		saved_powerctrl_2 = nvif_rd32(device, NV_PBUS_POWERCTRL_2);

	nv_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);		nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
	if (regoffset == 0x68) {		if (regoffset == 0x68) {
	saved_powerctrl_4 = nv_rd32(device, NV_PBUS_POWERCTRL_4);		saved_powerctrl_4 = nvif_rd32(device, NV_PBUS_POWERCTRL_4);
	nv_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);		nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
	}		}

	if (gpio) {		if (gpio) {
	@@ -316,8 +316,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput);		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput);
	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
	if (regoffset == 0x68)		if (regoffset == 0x68)
	nv_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);		nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
	nv_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);		nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);

	if (gpio) {		if (gpio) {
	gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1);		gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1);

drivers/gpu/drm/nouveau/dispnv04/dfp.c

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -281,7 +281,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
	struct drm_display_mode *adjusted_mode)		struct drm_display_mode *adjusted_mode)
	{		{
	struct drm_device *dev = encoder->dev;		struct drm_device *dev = encoder->dev;
	struct nouveau_device *device = nouveau_dev(dev);		struct nouveau_object *device = nouveau_drm(dev)->device;
	struct nouveau_drm *drm = nouveau_drm(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);		struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];		struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
	@@ -335,7 +335,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
	regp->fp_control \|= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;		regp->fp_control \|= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
	else /* gpu needs to scale */		else /* gpu needs to scale */
	regp->fp_control \|= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;		regp->fp_control \|= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
	if (nv_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)		if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
	regp->fp_control \|= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;		regp->fp_control \|= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
	if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&		if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
	output_mode->clock > 165000)		output_mode->clock > 165000)
	@@ -485,7 +485,7 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
	{		{
	#ifdef __powerpc__		#ifdef __powerpc__
	struct drm_device *dev = encoder->dev;		struct drm_device *dev = encoder->dev;
	struct nouveau_device *device = nouveau_dev(dev);		struct nouveau_object *device = nouveau_drm(dev)->device;

	/* BIOS scripts usually take care of the backlight, thanks		/* BIOS scripts usually take care of the backlight, thanks
	* Apple for your consistency.		* Apple for your consistency.

drivers/gpu/drm/nouveau/dispnv04/disp.h

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -171,8 +171,8 @@ static inline void
	nouveau_bios_run_init_table(struct drm_device *dev, u16 table,		nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
	struct dcb_output *outp, int crtc)		struct dcb_output *outp, int crtc)
	{		{
	struct nouveau_device *device = nouveau_dev(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_bios *bios = nouveau_bios(device);		struct nouveau_bios *bios = nouveau_bios(drm->device);
	struct nvbios_init init = {		struct nvbios_init init = {
	.subdev = nv_subdev(bios),		.subdev = nv_subdev(bios),
	.bios = bios,		.bios = bios,

drivers/gpu/drm/nouveau/dispnv04/hw.c

+23 −23

Original line number	Original line	Diff line number	Diff line
	@@ -168,7 +168,7 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
	struct nouveau_pll_vals *pllvals)		struct nouveau_pll_vals *pllvals)
	{		{
	struct nouveau_drm *drm = nouveau_drm(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_device *device = nv_device(drm->device);		struct nouveau_object *device = drm->device;
	struct nouveau_bios *bios = nouveau_bios(device);		struct nouveau_bios *bios = nouveau_bios(device);
	uint32_t reg1, pll1, pll2 = 0;		uint32_t reg1, pll1, pll2 = 0;
	struct nvbios_pll pll_lim;		struct nvbios_pll pll_lim;
	@@ -178,13 +178,13 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
	if (ret \|\| !(reg1 = pll_lim.reg))		if (ret \|\| !(reg1 = pll_lim.reg))
	return -ENOENT;		return -ENOENT;

	pll1 = nv_rd32(device, reg1);		pll1 = nvif_rd32(device, reg1);
	if (reg1 <= 0x405c)		if (reg1 <= 0x405c)
	pll2 = nv_rd32(device, reg1 + 4);		pll2 = nvif_rd32(device, reg1 + 4);
	else if (nv_two_reg_pll(dev)) {		else if (nv_two_reg_pll(dev)) {
	uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);		uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);

	pll2 = nv_rd32(device, reg2);		pll2 = nvif_rd32(device, reg2);
	}		}

	if (nv_device(drm->device)->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {		if (nv_device(drm->device)->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
	@@ -255,7 +255,7 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
	*/		*/

	struct nouveau_drm *drm = nouveau_drm(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_device *device = nv_device(drm->device);		struct nouveau_object *device = drm->device;
	struct nouveau_clock *clk = nouveau_clock(device);		struct nouveau_clock *clk = nouveau_clock(device);
	struct nouveau_bios *bios = nouveau_bios(device);		struct nouveau_bios *bios = nouveau_bios(device);
	struct nvbios_pll pll_lim;		struct nvbios_pll pll_lim;
	@@ -663,7 +663,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
	struct nv04_mode_state *state)		struct nv04_mode_state *state)
	{		{
	struct nouveau_drm *drm = nouveau_drm(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_device *device = nv_device(drm->device);		struct nouveau_object *device = drm->device;
	struct nouveau_timer *ptimer = nouveau_timer(device);		struct nouveau_timer *ptimer = nouveau_timer(device);
	struct nouveau_fb *pfb = nouveau_fb(device);		struct nouveau_fb *pfb = nouveau_fb(device);
	struct nv04_crtc_reg *regp = &state->crtc_reg[head];		struct nv04_crtc_reg *regp = &state->crtc_reg[head];
	@@ -678,15 +678,15 @@ nv_load_state_ext(struct drm_device *dev, int head,
	*/		*/
	NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);		NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);

	nv_wr32(device, NV_PVIDEO_STOP, 1);		nvif_wr32(device, NV_PVIDEO_STOP, 1);
	nv_wr32(device, NV_PVIDEO_INTR_EN, 0);		nvif_wr32(device, NV_PVIDEO_INTR_EN, 0);
	nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);		nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
	nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);		nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
	nv_wr32(device, NV_PVIDEO_LIMIT(0), pfb->ram->size - 1);		nvif_wr32(device, NV_PVIDEO_LIMIT(0), pfb->ram->size - 1);
	nv_wr32(device, NV_PVIDEO_LIMIT(1), pfb->ram->size - 1);		nvif_wr32(device, NV_PVIDEO_LIMIT(1), pfb->ram->size - 1);
	nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1);		nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1);
	nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1);		nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1);
	nv_wr32(device, NV_PBUS_POWERCTRL_2, 0);		nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);

	NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);		NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
	NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);		NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
	@@ -769,15 +769,15 @@ static void
	nv_save_state_palette(struct drm_device *dev, int head,		nv_save_state_palette(struct drm_device *dev, int head,
	struct nv04_mode_state *state)		struct nv04_mode_state *state)
	{		{
	struct nouveau_device *device = nouveau_dev(dev);		struct nouveau_object *device = nouveau_drm(dev)->device;
	int head_offset = head * NV_PRMDIO_SIZE, i;		int head_offset = head * NV_PRMDIO_SIZE, i;

	nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,		nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
	NV_PRMDIO_PIXEL_MASK_MASK);		NV_PRMDIO_PIXEL_MASK_MASK);
	nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);		nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);

	for (i = 0; i < 768; i++) {		for (i = 0; i < 768; i++) {
	state->crtc_reg[head].DAC[i] = nv_rd08(device,		state->crtc_reg[head].DAC[i] = nvif_rd08(device,
	NV_PRMDIO_PALETTE_DATA + head_offset);		NV_PRMDIO_PALETTE_DATA + head_offset);
	}		}

	@@ -788,15 +788,15 @@ void
	nouveau_hw_load_state_palette(struct drm_device *dev, int head,		nouveau_hw_load_state_palette(struct drm_device *dev, int head,
	struct nv04_mode_state *state)		struct nv04_mode_state *state)
	{		{
	struct nouveau_device *device = nouveau_dev(dev);		struct nouveau_object *device = nouveau_drm(dev)->device;
	int head_offset = head * NV_PRMDIO_SIZE, i;		int head_offset = head * NV_PRMDIO_SIZE, i;

	nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,		nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
	NV_PRMDIO_PIXEL_MASK_MASK);		NV_PRMDIO_PIXEL_MASK_MASK);
	nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);		nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);

	for (i = 0; i < 768; i++) {		for (i = 0; i < 768; i++) {
	nv_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,		nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,
	state->crtc_reg[head].DAC[i]);		state->crtc_reg[head].DAC[i]);
	}		}