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Commit da40ff48 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: cache boot reporting updates 



* print aliasing or not, VIPT/PIPT etc
* compress param storage using bitfields
* more use of IS_ENABLED to de-uglify code

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 590892de

arch/arc/include/asm/arcregs.h

+1 −1
Original line number Diff line number Diff line
@@ -296,7 +296,7 @@ struct cpuinfo_arc_mmu { 
};



struct cpuinfo_arc_cache {

	unsigned int sz, line_len, assoc, ver;

	unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6;

};



struct cpuinfo_arc_ccm {

arch/arc/mm/cache_arc700.c

+36 −25
Original line number Diff line number Diff line
@@ -77,21 +77,19 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len) 
{

	int n = 0;



#define PR_CACHE(p, enb, str)						\

{									\

#define PR_CACHE(p, cfg, str)						\

	if (!(p)->ver)							\

		n += scnprintf(buf + n, len - n, str"\t\t: N/A\n");	\

	else								\

		n += scnprintf(buf + n, len - n,			\

			str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \

			TO_KB((p)->sz), (p)->assoc, (p)->line_len,	\

			enb ?  "" : "DISABLED (kernel-build)");		\

}

			str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n",	\

			(p)->sz_k, (p)->assoc, (p)->line_len,		\

			(p)->vipt ? "VIPT" : "PIPT",			\

			(p)->alias ? " aliasing" : "",			\

			IS_ENABLED(cfg) ? "" : " (not used)");



	PR_CACHE(&cpuinfo_arc700[c].icache, IS_ENABLED(CONFIG_ARC_HAS_ICACHE),

			"I-Cache");

	PR_CACHE(&cpuinfo_arc700[c].dcache, IS_ENABLED(CONFIG_ARC_HAS_DCACHE),

			"D-Cache");

	PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache");

	PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache");



	return buf;

}
@@ -116,20 +114,31 @@ void read_decode_cache_bcr(void) 
	p_ic = &cpuinfo_arc700[cpu].icache;

	READ_BCR(ARC_REG_IC_BCR, ibcr);



	if (!ibcr.ver)

		goto dc_chk;



	BUG_ON(ibcr.config != 3);

	p_ic->assoc = 2;		/* Fixed to 2w set assoc */

	p_ic->line_len = 8 << ibcr.line_len;

	p_ic->sz = 0x200 << ibcr.sz;

	p_ic->sz_k = 1 << (ibcr.sz - 1);

	p_ic->ver = ibcr.ver;

	p_ic->vipt = 1;

	p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1;



dc_chk:

	p_dc = &cpuinfo_arc700[cpu].dcache;

	READ_BCR(ARC_REG_DC_BCR, dbcr);



	if (!dbcr.ver)

		return;



	BUG_ON(dbcr.config != 2);

	p_dc->assoc = 4;		/* Fixed to 4w set assoc */

	p_dc->line_len = 16 << dbcr.line_len;

	p_dc->sz = 0x200 << dbcr.sz;

	p_dc->sz_k = 1 << (dbcr.sz - 1);

	p_dc->ver = dbcr.ver;

	p_dc->vipt = 1;

	p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1;

}



/*
@@ -142,14 +151,16 @@ void read_decode_cache_bcr(void) 
void arc_cache_init(void)

{

	unsigned int __maybe_unused cpu = smp_processor_id();

	struct cpuinfo_arc_cache __maybe_unused *ic, __maybe_unused *dc;

	char str[256];



	printk(arc_cache_mumbojumbo(0, str, sizeof(str)));



#ifdef CONFIG_ARC_HAS_ICACHE

	ic = &cpuinfo_arc700[cpu].icache;

	if (ic->ver) {

	if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {

		struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;



		if (!ic->ver)

			panic("cache support enabled but non-existent cache\n");



		if (ic->line_len != L1_CACHE_BYTES)

			panic("ICache line [%d] != kernel Config [%d]",

			      ic->line_len, L1_CACHE_BYTES);
@@ -158,26 +169,26 @@ void arc_cache_init(void) 
			panic("Cache ver [%d] doesn't match MMU ver [%d]\n",

			      ic->ver, CONFIG_ARC_MMU_VER);

	}

#endif



#ifdef CONFIG_ARC_HAS_DCACHE

	dc = &cpuinfo_arc700[cpu].dcache;

	if (dc->ver) {

		unsigned int dcache_does_alias;

	if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {

		struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;

		int handled;



		if (!dc->ver)

			panic("cache support enabled but non-existent cache\n");



		if (dc->line_len != L1_CACHE_BYTES)

			panic("DCache line [%d] != kernel Config [%d]",

			      dc->line_len, L1_CACHE_BYTES);



		/* check for D-Cache aliasing */

		dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;

		handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);



		if (dcache_does_alias && !cache_is_vipt_aliasing())

		if (dc->alias && !handled)

			panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");

		else if (!dcache_does_alias && cache_is_vipt_aliasing())

		else if (!dc->alias && handled)

			panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");

	}

#endif

}



#define OP_INV		0x1