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Commit d9ffa6c2 authored by Mike McCormack's avatar Mike McCormack Committed by Greg Kroah-Hartman
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staging: rtl8192e: Pass r8192e_priv to phy functions 



Phy functions shouldn't be associated with net_device.

Signed-off-by: default avatarMike McCormack <mikem@ring3k.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 5aa68752

drivers/staging/rtl8192e/r8190_rtl8256.c

+43 −46
Original line number Diff line number Diff line
@@ -23,15 +23,14 @@ 
 * Return:      NONE

 * Note:	8226 support both 20M  and 40 MHz

 *---------------------------------------------------------------------------*/

void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)	//20M or 40M

void PHY_SetRF8256Bandwidth(struct r8192_priv *priv, HT_CHANNEL_WIDTH Bandwidth)	//20M or 40M

{

	u8	eRFPath;

	struct r8192_priv *priv = ieee80211_priv(dev);



	//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)

	for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)

	{

		if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))

		if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))

				continue;



		switch(Bandwidth)
@@ -39,9 +38,9 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) 
			case HT_CHANNEL_WIDTH_20:

				if(priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later!

				{

					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba

					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);

					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);

					rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba

					rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);

					rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);



					//cosa add for sd3's request 01/23/2008

					//rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
@@ -55,9 +54,9 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) 
			case HT_CHANNEL_WIDTH_20_40:

				if(priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later!

				{

					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba

					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff);

					rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1);

					rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba

					rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff);

					rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1);



				}

				else
@@ -80,43 +79,43 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) 
 * Output:      NONE

 * Return:      NONE

 *---------------------------------------------------------------------------*/

RT_STATUS PHY_RF8256_Config(struct net_device* dev)

RT_STATUS PHY_RF8256_Config(struct r8192_priv *priv)

{

	struct r8192_priv *priv = ieee80211_priv(dev);

	// Initialize general global value

	//

	RT_STATUS rtStatus = RT_STATUS_SUCCESS;

	// TODO: Extend RF_PATH_C and RF_PATH_D in the future

	priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;

	// Config BB and RF

	rtStatus = phy_RF8256_Config_ParaFile(dev);

	rtStatus = phy_RF8256_Config_ParaFile(priv);



	return rtStatus;

}



/*--------------------------------------------------------------------------

 * Overview:    Interface to config 8256

 * Input:       struct net_device*	dev

 * Output:      NONE

 * Return:      NONE

 *---------------------------------------------------------------------------*/

RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev)

RT_STATUS phy_RF8256_Config_ParaFile(struct r8192_priv *priv)

{

	u32 	u4RegValue = 0;

	u8 	eRFPath;

	RT_STATUS				rtStatus = RT_STATUS_SUCCESS;

	BB_REGISTER_DEFINITION_T	*pPhyReg;

	struct r8192_priv *priv = ieee80211_priv(dev);

	u32	RegOffSetToBeCheck = 0x3;

	u32 	RegValueToBeCheck = 0x7f1;

	u32	RF3_Final_Value = 0;

	u8	ConstRetryTimes = 5, RetryTimes = 5;

	u8 ret = 0;



	//3//-----------------------------------------------------------------

	//3// <2> Initialize RF

	//3//-----------------------------------------------------------------

	for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)

	{

		if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))

		if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))

				continue;



		pPhyReg = &priv->PHYRegDef[eRFPath];
@@ -126,29 +125,29 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev) 
		{

		case RF90_PATH_A:

		case RF90_PATH_C:

			u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);

			u4RegValue = rtl8192_QueryBBReg(priv, pPhyReg->rfintfs, bRFSI_RFENV);

			break;

		case RF90_PATH_B :

		case RF90_PATH_D:

			u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);

			u4RegValue = rtl8192_QueryBBReg(priv, pPhyReg->rfintfs, bRFSI_RFENV<<16);

			break;

		}



		/*----Set RF_ENV enable----*/

		rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);

		rtl8192_setBBreg(priv, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);



		/*----Set RF_ENV output high----*/

		rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);

		rtl8192_setBBreg(priv, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);



		/* Set bit number of Address and Data for RF register */

		rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); 	// Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258

		rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);	// Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???

		rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); 	// Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258

		rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);	// Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???



		rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);

		rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);



		/*----Check RF block (for FPGA platform only)----*/

		// TODO: this function should be removed on ASIC , Emily 2007.2.2

		rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath);

		rtStatus = rtl8192_phy_checkBBAndRF(priv, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath);

		if(rtStatus!= RT_STATUS_SUCCESS)

		{

			RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
@@ -163,8 +162,8 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev) 
		case RF90_PATH_A:

			while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)

			{

				ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);

				RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);

				ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);

				RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);

				RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);

				RetryTimes--;

			}
@@ -172,8 +171,8 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev) 
		case RF90_PATH_B:

			while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)

			{

				ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);

				RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);

				ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);

				RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);

				RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);

				RetryTimes--;

			}
@@ -181,8 +180,8 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev) 
		case RF90_PATH_C:

			while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)

			{

				ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);

				RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);

				ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);

				RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);

				RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);

				RetryTimes--;

			}
@@ -190,8 +189,8 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev) 
		case RF90_PATH_D:

			while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)

			{

				ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);

				RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);

				ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);

				RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);

				RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);

				RetryTimes--;

			}
@@ -203,11 +202,11 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev) 
		{

		case RF90_PATH_A:

		case RF90_PATH_C:

			rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);

			rtl8192_setBBreg(priv, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);

			break;

		case RF90_PATH_B :

		case RF90_PATH_D:

			rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);

			rtl8192_setBBreg(priv, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);

			break;

		}
@@ -227,10 +226,9 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev) 
}





void PHY_SetRF8256CCKTxPower(struct net_device*	dev, u8	powerlevel)

void PHY_SetRF8256CCKTxPower(struct r8192_priv *priv, u8 powerlevel)

{

	u32	TxAGC=0;

	struct r8192_priv *priv = ieee80211_priv(dev);



	TxAGC = powerlevel;

	if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
@@ -242,13 +240,12 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) 
	}

	if(TxAGC > 0x24)

		TxAGC = 0x24;

	rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);

	rtl8192_setBBreg(priv, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);

}





void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)

void PHY_SetRF8256OFDMTxPower(struct r8192_priv *priv, u8 powerlevel)

{

	struct r8192_priv *priv = ieee80211_priv(dev);



	u32 writeVal, powerBase0, powerBase1, writeVal_tmp;

	u8 index = 0;
@@ -290,7 +287,7 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) 
		{

			writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;

		}

		rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);

		rtl8192_setBBreg(priv, RegOffset[index], 0x7f7f7f7f, writeVal);

	}

}
@@ -356,22 +353,22 @@ SetRFPowerState8190(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState) 
			write_nic_byte(priv, ANAPAR, 0x37);//160MHz

			mdelay(1);

			//enable clock 80/88 MHz

			rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]

			rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]

			priv->bHwRfOffAction = 0;



			//RF-A, RF-B

			//enable RF-Chip A/B

			rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1);		// 0x860[4]

			rtl8192_setBBreg(priv, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1);		// 0x860[4]

			//analog to digital on

			rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]

			rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]

			//digital to analog on

			rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]

			rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]

			//rx antenna on

			rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]

			rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]

			//rx antenna on

			rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]

			rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]

			//analog to digital part2 on

			rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); 	// 0x880[6:5]

			rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x60, 0x3); 	// 0x880[6:5]



		}

drivers/staging/rtl8192e/r8190_rtl8256.h

+5 −5
Original line number Diff line number Diff line
@@ -12,15 +12,15 @@ 


#define RTL819X_TOTAL_RF_PATH 2 /* for 8192E */



void PHY_SetRF8256Bandwidth(struct net_device *dev,

void PHY_SetRF8256Bandwidth(struct r8192_priv *priv,

				   HT_CHANNEL_WIDTH Bandwidth);



RT_STATUS PHY_RF8256_Config(struct net_device *dev);

RT_STATUS PHY_RF8256_Config(struct r8192_priv *priv);



RT_STATUS phy_RF8256_Config_ParaFile(struct net_device *dev);

RT_STATUS phy_RF8256_Config_ParaFile(struct r8192_priv *priv);



void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel);

void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel);

void PHY_SetRF8256CCKTxPower(struct r8192_priv *priv, u8 powerlevel);

void PHY_SetRF8256OFDMTxPower(struct r8192_priv *priv, u8 powerlevel);



bool MgntActSet_RF_State(struct net_device *dev,

				RT_RF_POWER_STATE StateToSet,

drivers/staging/rtl8192e/r8192E_core.c

+20 −20
Original line number Diff line number Diff line
@@ -752,18 +752,18 @@ void PHY_SetRtl8192eRfOff(struct net_device* dev) 
	struct r8192_priv *priv = ieee80211_priv(dev);



	//disable RF-Chip A/B

	rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);

	rtl8192_setBBreg(priv, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);

	//analog to digital off, for power save

	rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);

	rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x0);

	//digital to analog off, for power save

	rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);

	rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x18, 0x0);

	//rx antenna off

	rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);

	rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0xf, 0x0);

	//rx antenna off

	rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);

	rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0xf, 0x0);

	//analog to digital part2 off, for power save

	rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);

	rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);

	rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x60, 0x0);

	rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x4, 0x0);

	// Analog parameter!!Change bias and Lbus control.

	write_nic_byte(priv, ANAPAR_FOR_8192PciE, 0x07);
@@ -2659,7 +2659,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev) 
	//3// Initialize BB before MAC

	//3//

	RT_TRACE(COMP_INIT, "BB Config Start!\n");

	rtStatus = rtl8192_BBConfig(dev);

	rtStatus = rtl8192_BBConfig(priv);

	if(rtStatus != RT_STATUS_SUCCESS)

	{

		RT_TRACE(COMP_ERR, "BB Config failed\n");
@@ -2768,11 +2768,11 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev) 
	//2=======================================================

	// Set PHY related configuration defined in MAC register bank

	//2=======================================================

	rtl8192_phy_configmac(dev);

	rtl8192_phy_configmac(priv);



	if (priv->card_8192_version > (u8) VERSION_8190_BD) {

		rtl8192_phy_getTxPower(dev);

		rtl8192_phy_setTxPower(dev, priv->chan);

		rtl8192_phy_getTxPower(priv);

		rtl8192_phy_setTxPower(priv, priv->chan);

	}



	//if D or C cut
@@ -2811,7 +2811,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev) 
	if(priv->ResetProgress == RESET_TYPE_NORESET)

	{

	RT_TRACE(COMP_INIT, "RF Config Started!\n");

	rtStatus = rtl8192_phy_RFConfig(dev);

	rtStatus = rtl8192_phy_RFConfig(priv);

	if(rtStatus != RT_STATUS_SUCCESS)

	{

		RT_TRACE(COMP_ERR, "RF Config failed\n");
@@ -2819,11 +2819,11 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev) 
	}

	RT_TRACE(COMP_INIT, "RF Config Finished!\n");

	}

	rtl8192_phy_updateInitGain(dev);

	rtl8192_phy_updateInitGain(priv);



	/*---- Set CCK and OFDM Block "ON"----*/

	rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);

	rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);

	rtl8192_setBBreg(priv, rFPGA0_RFMOD, bCCKEn, 0x1);

	rtl8192_setBBreg(priv, rFPGA0_RFMOD, bOFDMEn, 0x1);



	//Enable Led

	write_nic_byte(priv, 0x87, 0x0);
@@ -2864,8 +2864,8 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev) 


		if(priv->IC_Cut >= IC_VersionCut_D)

		{

			tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord);

			tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord);

			tmpRegA = rtl8192_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord);

			tmpRegC = rtl8192_QueryBBReg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord);

			for(i = 0; i<TxBBGainTableLength; i++)

			{

				if(tmpRegA == priv->txbbgain_table[i].txbbgain_value)
@@ -2877,7 +2877,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev) 
				}

			}



		TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);

		TempCCk = rtl8192_QueryBBReg(priv, rCCK0_TxFilter1, bMaskByte2);



		for(i=0 ; i<CCKTxBBGainTableLength ; i++)

		{
@@ -3873,7 +3873,7 @@ static void rtl8192_process_phyinfo(struct r8192_priv * priv, u8* buffer,struct 
	{

		for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++)

		{

			if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, rfpath))

			if (!rtl8192_phy_CheckIsLegalRFPath(priv, rfpath))

				continue;

			RT_TRACE(COMP_DBG, "pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n", pprevious_stats->RxMIMOSignalStrength[rfpath]);

			//Fixed by Jacken 2008-03-20
@@ -4125,7 +4125,7 @@ static void rtl8192_query_rxphystatus( 
	/*2007.08.30 requested by SD3 Jerry */

	if (priv->phy_check_reg824 == 0)

	{

		priv->phy_reg824_bit9 = rtl8192_QueryBBReg(priv->ieee80211->dev, rFPGA0_XA_HSSIParameter2, 0x200);

		priv->phy_reg824_bit9 = rtl8192_QueryBBReg(priv, rFPGA0_XA_HSSIParameter2, 0x200);

		priv->phy_check_reg824 = 1;

	}

drivers/staging/rtl8192e/r8192E_dm.c

+42 −42

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drivers/staging/rtl8192e/r819xE_phy.c

+130 −154

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