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Commit d96a9804 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
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[ARM] 4986/1: S3C24XX: Simtec machines need UCLK as parent to DCLK



All current Simtec designs source the DCLK outputs from
the UPLL. This means the DCLK's parent must be set to UPLL
so that anything enabling and disabling an UPLL sourced
clock does not shutdown the DCLK due to missing open counts.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 1017be88
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+2 −2
Original line number Diff line number Diff line
@@ -592,10 +592,10 @@ static void __init bast_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = NULL;
	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = NULL;
	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
+1 −1
Original line number Diff line number Diff line
@@ -393,7 +393,7 @@ static void __init vr1000_map_io(void)
{
	/* initialise clock sources */

	s3c24xx_dclk0.parent = NULL;
	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = NULL;
+2 −2
Original line number Diff line number Diff line
@@ -413,10 +413,10 @@ static void __init anubis_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = NULL;
	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = NULL;
	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
+3 −2
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/clk.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -344,10 +345,10 @@ static void __init osiris_map_io(void)

	/* initialise the clocks */

	s3c24xx_dclk0.parent = NULL;
	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = NULL;
	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;