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Commit d94bc4fc authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: relax ioremap prohibition (309caa9c) for -final and -stable
  ARM: 6440/1: ep93xx: DMA: fix channel_disable
  cpuimx27: fix i2c bus selection
  cpuimx27: fix compile when ULPI is selected
  ARM: 6435/1: Fix HWCAP_TLS flag for ARM11MPCore/Cortex-A9
  ARM: 6436/1: AT91: Fix power-saving in idle-mode on 926T processors
  ARM: fix section mismatch warnings in Versatile Express
  ARM: 6412/1: kprobes-decode: add support for MOVW instruction
  ARM: 6419/1: mmu: Fix MT_MEMORY and MT_MEMORY_NONCACHED pte flags
  ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to data corruption
parents 70813196 06c10884

arch/arm/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -1101,6 +1101,20 @@ config ARM_ERRATA_720789 
	  invalidated are not, resulting in an incoherency in the system page

	  tables. The workaround changes the TLB flushing routines to invalidate

	  entries regardless of the ASID.



config ARM_ERRATA_743622

	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"

	depends on CPU_V7

	help

	  This option enables the workaround for the 743622 Cortex-A9

	  (r2p0..r2p2) erratum. Under very rare conditions, a faulty

	  optimisation in the Cortex-A9 Store Buffer may lead to data

	  corruption. This workaround sets a specific bit in the diagnostic

	  register of the Cortex-A9 which disables the Store Buffer

	  optimisation, preventing the defect from occurring. This has no

	  visible impact on the overall performance or power consumption of the

	  processor.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/kernel/kprobes-decode.c

+4 −3
Original line number Diff line number Diff line
@@ -1162,11 +1162,12 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) 
{

	/*

	 * MSR   : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx

	 * Undef : cccc 0011 0x00 xxxx xxxx xxxx xxxx xxxx

	 * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx

	 * ALU op with S bit and Rd == 15 :

	 *	   cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx

	 */

	if ((insn & 0x0f900000) == 0x03200000 ||	/* MSR & Undef */

	if ((insn & 0x0fb00000) == 0x03200000 ||	/* MSR */

	    (insn & 0x0ff00000) == 0x03400000 ||	/* Undef */

	    (insn & 0x0e10f000) == 0x0210f000)		/* ALU s-bit, R15  */

		return INSN_REJECTED;
@@ -1177,7 +1178,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) 
	 * *S (bit 20) updates condition codes

	 * ADC/SBC/RSC reads the C flag

	 */

	insn &= 0xfff00fff;	/* Rn = r0, Rd = r0 */

	insn &= 0xffff0fff;	/* Rd = r0 */

	asi->insn[0] = insn;

	asi->insn_handler = (insn & (1 << 20)) ?  /* S-bit */

			emulate_alu_imm_rwflags : emulate_alu_imm_rflags;

arch/arm/mach-at91/include/mach/system.h

+3 −4
Original line number Diff line number Diff line
@@ -28,17 +28,16 @@ 


static inline void arch_idle(void)

{

#ifndef CONFIG_DEBUG_KERNEL

	/*

	 * Disable the processor clock.  The processor will be automatically

	 * re-enabled by an interrupt or by a reset.

	 */

	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);

#else

#ifndef CONFIG_CPU_ARM920T

	/*

	 * Set the processor (CP15) into 'Wait for Interrupt' mode.

	 * Unlike disabling the processor clock via the PMC (above)

	 *  this allows the processor to be woken via JTAG.

	 * Post-RM9200 processors need this in conjunction with the above

	 * to save power when idle.

	 */

	cpu_do_idle();

#endif

arch/arm/mach-ep93xx/dma-m2p.c

+1 −1
Original line number Diff line number Diff line
@@ -276,7 +276,7 @@ static void channel_disable(struct m2p_channel *ch) 
	v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);

	m2p_set_control(ch, v);



	while (m2p_channel_state(ch) == STATE_ON)

	while (m2p_channel_state(ch) >= STATE_ON)

		cpu_relax();



	m2p_set_control(ch, 0x0);

arch/arm/mach-imx/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -122,6 +122,7 @@ config MACH_CPUIMX27 
	select IMX_HAVE_PLATFORM_IMX_I2C

	select IMX_HAVE_PLATFORM_IMX_UART

	select IMX_HAVE_PLATFORM_MXC_NAND

	select MXC_ULPI if USB_ULPI

	help

	  Include support for Eukrea CPUIMX27 platform. This includes

	  specific configurations for the module and its peripherals.