perf vendor events: Add IvyTown V19 event file (d910f0ba) · Commits · e / devices / android_kernel_teracube_emerald

tools/perf/pmu-events/arch/x86/ivytown/cache.json

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tools/perf/pmu-events/arch/x86/ivytown/floating-point.json

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		[
		{
		"PublicDescription": "Counts number of X87 uops executed.",
		"EventCode": "0x10",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "FP_COMP_OPS_EXE.X87",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
		"EventCode": "0x10",
		"Counter": "0,1,2,3",
		"UMask": "0x10",
		"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
		"EventCode": "0x10",
		"Counter": "0,1,2,3",
		"UMask": "0x20",
		"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
		"EventCode": "0x10",
		"Counter": "0,1,2,3",
		"UMask": "0x40",
		"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
		"EventCode": "0x10",
		"Counter": "0,1,2,3",
		"UMask": "0x80",
		"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",
		"EventCode": "0x11",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "SIMD_FP_256.PACKED_SINGLE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
		"EventCode": "0x11",
		"Counter": "0,1,2,3",
		"UMask": "0x2",
		"EventName": "SIMD_FP_256.PACKED_DOUBLE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
		"EventCode": "0xC1",
		"Counter": "0,1,2,3",
		"UMask": "0x8",
		"EventName": "OTHER_ASSISTS.AVX_STORE",
		"SampleAfterValue": "100003",
		"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"EventCode": "0xC1",
		"Counter": "0,1,2,3",
		"UMask": "0x10",
		"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
		"SampleAfterValue": "100003",
		"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"EventCode": "0xC1",
		"Counter": "0,1,2,3",
		"UMask": "0x20",
		"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
		"SampleAfterValue": "100003",
		"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of X87 FP assists due to output values.",
		"EventCode": "0xCA",
		"Counter": "0,1,2,3",
		"UMask": "0x2",
		"EventName": "FP_ASSIST.X87_OUTPUT",
		"SampleAfterValue": "100003",
		"BriefDescription": "Number of X87 assists due to output value.",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of X87 FP assists due to input values.",
		"EventCode": "0xCA",
		"Counter": "0,1,2,3",
		"UMask": "0x4",
		"EventName": "FP_ASSIST.X87_INPUT",
		"SampleAfterValue": "100003",
		"BriefDescription": "Number of X87 assists due to input value.",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of SIMD FP assists due to output values.",
		"EventCode": "0xCA",
		"Counter": "0,1,2,3",
		"UMask": "0x8",
		"EventName": "FP_ASSIST.SIMD_OUTPUT",
		"SampleAfterValue": "100003",
		"BriefDescription": "Number of SIMD FP assists due to Output values",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of SIMD FP assists due to input values.",
		"EventCode": "0xCA",
		"Counter": "0,1,2,3",
		"UMask": "0x10",
		"EventName": "FP_ASSIST.SIMD_INPUT",
		"SampleAfterValue": "100003",
		"BriefDescription": "Number of SIMD FP assists due to input values",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Cycles with any input/output SSE* or FP assists.",
		"EventCode": "0xCA",
		"Counter": "0,1,2,3",
		"UMask": "0x1e",
		"EventName": "FP_ASSIST.ANY",
		"SampleAfterValue": "100003",
		"BriefDescription": "Cycles with any input/output SSE or FP assist",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3"
		}
		]
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tools/perf/pmu-events/arch/x86/ivytown/frontend.json

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		[
		{
		"PublicDescription": "Counts cycles the IDQ is empty.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x2",
		"EventName": "IDQ.EMPTY",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x4",
		"EventName": "IDQ.MITE_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x8",
		"EventName": "IDQ.DSB_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x10",
		"EventName": "IDQ.MS_DSB_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x20",
		"EventName": "IDQ.MS_MITE_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x30",
		"EventName": "IDQ.MS_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x30",
		"EventName": "IDQ.MS_CYCLES",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x4",
		"EventName": "IDQ.MITE_CYCLES",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x8",
		"EventName": "IDQ.DSB_CYCLES",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x10",
		"EventName": "IDQ.MS_DSB_CYCLES",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x10",
		"EdgeDetect": "1",
		"EventName": "IDQ.MS_DSB_OCCUR",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x18",
		"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
		"CounterMask": "4",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x18",
		"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x24",
		"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles MITE is delivering 4 Uops",
		"CounterMask": "4",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x24",
		"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles MITE is delivering any Uop",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of uops delivered to IDQ from any path.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x3c",
		"EventName": "IDQ.MITE_ALL_UOPS",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
		"EventCode": "0x80",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "ICACHE.HIT",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
		"EventCode": "0x80",
		"Counter": "0,1,2,3",
		"UMask": "0x2",
		"EventName": "ICACHE.MISSES",
		"SampleAfterValue": "200003",
		"BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
		"EventCode": "0x80",
		"Counter": "0,1,2,3",
		"UMask": "0x4",
		"EventName": "ICACHE.IFETCH_STALL",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
		"EventCode": "0x9C",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0x9C",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
		"CounterMask": "4",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0x9C",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
		"CounterMask": "3",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0x9C",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
		"CounterMask": "2",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0x9C",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0x9C",
		"Invert": "1",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"PublicDescription": "Number of DSB to MITE switches.",
		"EventCode": "0xAB",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "DSB2MITE_SWITCHES.COUNT",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Cycles DSB to MITE switches caused delay.",
		"EventCode": "0xAB",
		"Counter": "0,1,2,3",
		"UMask": "0x2",
		"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "DSB Fill encountered > 3 DSB lines.",
		"EventCode": "0xAC",
		"Counter": "0,1,2,3",
		"UMask": "0x8",
		"EventName": "DSB_FILL.EXCEED_DSB_LINES",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
		"EventCode": "0x79",
		"Counter": "0,1,2,3",
		"UMask": "0x30",
		"EdgeDetect": "1",
		"EventName": "IDQ.MS_SWITCHES",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		}
		]
		No newline at end of file

tools/perf/pmu-events/arch/x86/ivytown/memory.json

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tools/perf/pmu-events/arch/x86/ivytown/other.json

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		[
		{
		"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
		"EventCode": "0x5C",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "CPL_CYCLES.RING0",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
		"EventCode": "0x5C",
		"Counter": "0,1,2,3",
		"UMask": "0x2",
		"EventName": "CPL_CYCLES.RING123",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Number of intervals between processor halts while thread is in ring 0.",
		"EventCode": "0x5C",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EdgeDetect": "1",
		"EventName": "CPL_CYCLES.RING0_TRANS",
		"SampleAfterValue": "100007",
		"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
		"CounterMask": "1",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
		"EventCode": "0x63",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
		"SampleAfterValue": "2000003",
		"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		}
		]
		No newline at end of file