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Commit d8e7943d authored by Paul Mundt's avatar Paul Mundt
Browse files

Merge branch 'common/mmcif' into rmobile/mmcif

parents df73af86 22efa0fe

arch/sh/include/mach-common/mach/romimage.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -4,7 +4,7 @@ 




#else /* __ASSEMBLY__ */

#else /* __ASSEMBLY__ */





extern inline void mmcif_update_progress(int nr)

static inline void mmcif_update_progress(int nr)

{

{

}

}

arch/sh/include/mach-ecovec24/mach/romimage.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -35,7 +35,7 @@ 
#define HIZCRA		0xa4050158

#define HIZCRA		0xa4050158

#define PGDR		0xa405012c

#define PGDR		0xa405012c





extern inline void mmcif_update_progress(int nr)

static inline void mmcif_update_progress(int nr)

{

{

	/* disable Hi-Z for LED pins */

	/* disable Hi-Z for LED pins */

	__raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);

	__raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);

arch/sh/include/mach-kfr2r09/mach/romimage.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -23,7 +23,7 @@ 




#else /* __ASSEMBLY__ */

#else /* __ASSEMBLY__ */





extern inline void mmcif_update_progress(int nr)

static inline void mmcif_update_progress(int nr)

{

{

}

}

include/linux/mmc/sh_mmcif.h

+12 −14
Original line number Original line Diff line number Diff line
@@ -77,6 +77,9 @@ struct sh_mmcif_plat_data { 
#define CLK_ENABLE		(1 << 24) /* 1: output mmc clock */

#define CLK_ENABLE		(1 << 24) /* 1: output mmc clock */

#define CLK_CLEAR		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))

#define CLK_CLEAR		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))

#define CLK_SUP_PCLK		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))

#define CLK_SUP_PCLK		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))

#define CLKDIV_4		(1<<16) /* mmc clock frequency.

					 * n: bus clock/(2^(n+1)) */

#define CLKDIV_256		(7<<16) /* mmc clock frequency. (see above) */

#define SRSPTO_256		((1 << 13) | (0 << 12)) /* resp timeout */

#define SRSPTO_256		((1 << 13) | (0 << 12)) /* resp timeout */

#define SRBSYTO_29		((1 << 11) | (1 << 10) |	\

#define SRBSYTO_29		((1 << 11) | (1 << 10) |	\

				 (1 << 9) | (1 << 8)) /* resp busy timeout */

				 (1 << 9) | (1 << 8)) /* resp busy timeout */
@@ -87,7 +90,7 @@ struct sh_mmcif_plat_data { 




/* CE_VERSION */

/* CE_VERSION */

#define SOFT_RST_ON		(1 << 31)

#define SOFT_RST_ON		(1 << 31)

#define SOFT_RST_OFF		~SOFT_RST_ON

#define SOFT_RST_OFF		0





static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)

static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)

{

{
@@ -175,12 +178,9 @@ static inline int sh_mmcif_boot_do_read(void __iomem *base, 




static inline void sh_mmcif_boot_init(void __iomem *base)

static inline void sh_mmcif_boot_init(void __iomem *base)

{

{

	unsigned long tmp;



	/* reset */

	/* reset */

	tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);

	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);

	sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | SOFT_RST_ON);

	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);

	sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & SOFT_RST_OFF);





	/* byte swap */

	/* byte swap */

	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);

	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
@@ -188,14 +188,10 @@ static inline void sh_mmcif_boot_init(void __iomem *base) 
	/* Set block size in MMCIF hardware */

	/* Set block size in MMCIF hardware */

	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);

	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);





	/* Enable the clock, set it to Bus clock/256 (about 325Khz).

	/* Enable the clock, set it to Bus clock/256 (about 325Khz). */

	 * It is unclear where 0x70000 comes from or if it is even needed.

	 * It is there for byte-compatibility with code that is known to

	 * work.

	 */

	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,

	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,

			CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 |

			CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |

			SCCSTO_29 | 0x70000);

			SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);





	/* CMD0 */

	/* CMD0 */

	sh_mmcif_boot_cmd(base, 0x00000040, 0);

	sh_mmcif_boot_cmd(base, 0x00000040, 0);
@@ -220,7 +216,9 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base, 
	unsigned long tmp;

	unsigned long tmp;





	/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */

	/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */

	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);

	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,

			CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |

			SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);





	/* CMD9 - Get CSD */

	/* CMD9 - Get CSD */

	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);

	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);